Partitioned Data Processing Array With Clock Gating and Isolation
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Solution Overview
Problem
Existing integrated circuits (ICs) face challenges in managing computational tasks across multiple processors without interference, leading to potential errors and inefficiencies in power and clock management due to lack of partitioning and isolation mechanisms.
Innovation Solution
The ICs are designed with a data processing array that can be subdivided into multiple partitions, featuring programmable isolation logic to prevent cross-partition access, independent clock gating, and power management, allowing each partition to execute separate applications without interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processors are used to provide significant computational power and parallelism, then processing capability is improved, but interference between processors and lack of isolation lead to errors and inefficiencies
Solution Approach 1:
The data processing array is segmented into multiple isolated partitions, each capable of independent operation. Partition boundaries are enforced through isolation logic that prevents cross-partition access to memory and resources, eliminating interference while maintaining high computational throughput through parallel processing across partitions.
2Reliability
If isolation logic is programmed to prevent cross-partition access, then reliability is improved, but device complexity increases due to additional isolation mechanisms
Solution Approach 1:
The isolation logic is integrated into the existing memory interface circuitry, allowing the same hardware structures to serve dual purposes: normal memory access within partitions and isolation enforcement at partition boundaries. This universal approach provides reliable partition isolation without adding separate dedicated isolation hardware for each boundary.
3Productivity
If the entire DP array is powered on for processing, then productivity is improved, but energy consumption increases
Solution Approach 1:
Power delivery is segmented to match the partitioned architecture, with independent power control for each partition. This allows the system to activate only the specific partitions needed for current processing tasks, maintaining high productivity when required while significantly reducing power consumption during partial utilization scenarios.
4Speed
If clock signals are provided to all partitions simultaneously, then processing speed is improved, but energy waste occurs in idle partitions
Solution Approach 1:
Clock signal distribution is made dynamic and selective, with clock gating control that enables or disables clocking to specific partitions based on their operational state. Active partitions receive full-speed clock signals for maximum processing speed, while idle partitions have their clock signals gated off to eliminate unnecessary energy consumption.
Data Source
AI summary
An apparatus includes a data processing array having a plurality of array tiles. The plurality of array tiles include a plurality of compute tiles. The compute tiles include a core coupled to a random-access memory (RAM) in a same compute tile and to a RAM of at least one other compute tile. The data processing array is subdivided into a plurality of partitions. Each partition includes a plurality of array tiles including at least one of the plurality of compute tiles. The apparatus includes a plurality of clock gate circuits being programmable to selectively gate a clock signal provided to a respective one of the plurality of partitions.