Partitioned Data Processing Array With Tile Memory Isolation

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Solution Overview

Problem

Integrated circuits (ICs) face challenges in efficiently managing computational resources and isolating partitions within a data processing array to prevent interference between independent applications, leading to potential errors and power inefficiencies.

Innovation Solution

The implementation of a data processing array with programmable isolation logic between array tiles, allowing for subdivision into independent partitions, along with clock gate circuits and power management on a per-partition basis, enabling independent operation and resource optimization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the data processing array operates as a single unified system, then computational power and parallelism are maximized, but interference between independent applications occurs and data isolation is compromised

Engineering Contradiction:
Improvedata isolationVSAvoidpartition management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The data processing array is segmented into multiple independent partitions, each capable of executing independent applications. Partitioning logic divides the array into separate regions with defined boundaries, allowing simultaneous execution of multiple applications while preventing interference between them. Each partition has its own resource allocation and access controls.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Isolation logic acts as an intermediary mechanism between partitions, controlling and mediating access requests. The isolation logic intercepts memory access requests, checks partition boundaries, and either permits or blocks access based on the requesting partition's authorization, thereby preventing unauthorized cross-partition access while maintaining system-wide coordination.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the entire data processing array is powered on continuously, then computational resources are always available, but power consumption increases

Engineering Contradiction:
Improvecomputational availabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

Power management is made dynamic at the partition level, allowing the system to adapt power consumption to actual computational needs. Partitions can be independently powered on or off based on whether they are currently executing applications, enabling the system to maintain computational availability when needed while reducing power consumption during idle periods.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Power management is applied locally to individual partitions rather than uniformly across the entire array. Each partition can have its power state independently controlled, allowing selective activation of only those partitions currently needed for computation, thereby optimizing the balance between productivity and energy usage.

Inventive Principle:
Principle #3Local quality

3Ease of operation

If access control between array tiles is relaxed, then resource sharing and communication efficiency improve, but data security and partition isolation are compromised

Engineering Contradiction:
Improveresource sharing efficiencyVSAvoidpartition interference
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

Access control parameters are dynamically changed based on the operational state and authorization level of each partition. The isolation logic modifies access permissions in real-time, allowing efficient resource sharing within authorized boundaries while automatically tightening controls to prevent partition interference when boundary violations are detected or authorized.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11848670B2Multiple partitions in a data processing array
Publication Date: 2023.12.19 XILINX INC
  • US11848670B2 patent drawing
  • US11848670B2 patent drawing
  • US11848670B2 patent drawing

AI summary

An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.