Partitioned Data Processing Array With Tile RAM Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuits (ICs) face challenges in managing computational resources efficiently, particularly in multi-processor architectures, where interference between different applications executing in separate partitions can lead to errors and inefficient power consumption.
Innovation Solution
The ICs are designed with a data processing array that can be subdivided into multiple partitions, each with independent clock and power management, and isolation logic to prevent data interference between partitions, allowing for separate execution of applications and dynamic control of clock signals and power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple applications execute in separate partitions within a data processing array, then computational efficiency and power management are improved, but isolation logic and partition boundary management increase device complexity
Solution Approach 1:
The data processing array is divided into multiple independent partitions, each capable of executing separate applications. This segmentation allows independent power management and computational efficiency while maintaining isolation between partitions through dedicated boundary logic.
Solution Approach 2:
Isolation logic is introduced as an intermediary component at partition boundaries to prevent unauthorized access between partitions. This mediator enables multiple applications to run simultaneously in separate partitions while maintaining security and preventing interference, thus improving computational efficiency without requiring complete system redesign.
2Reliability
If isolation logic is programmed to prevent array tiles from accessing RAMs across partition boundaries, then data security and error prevention are improved, but memory access flexibility deteriorates
Solution Approach 1:
The isolation logic is implemented locally at each partition boundary rather than globally across the entire array. This allows memory access to be restricted only where needed at partition boundaries while maintaining full flexibility within each partition. The local implementation prevents data leakage between partitions while preserving ease of operation for legitimate memory access patterns.
3Loss of energy
If clock signals are gated independently for each partition, then power consumption is reduced, but clock distribution complexity increases
Solution Approach 1:
Clock signal distribution is made dynamic through programmable clock gate circuits that can independently enable or disable clock signals to each partition based on operational requirements. This dynamic control allows the system to reduce power consumption by gating clocks to inactive partitions while maintaining the ability to quickly activate them when needed, without requiring permanent complex wiring.
4Use of energy by moving object
If the data processing array is subdivided into multiple partitions with independent power domains, then power management efficiency is improved, but the number of power domains and control circuits increases
Solution Approach 1:
The partitioning infrastructure serves multiple functions simultaneously: it enables independent power management, provides data isolation between applications, and supports flexible clock distribution. By creating a universal partitioning framework that handles all these functions through the same structural divisions and control mechanisms, the patent avoids the need for separate dedicated systems for each function, thus improving power management efficiency without proportionally increasing overall complexity.
Data Source
AI summary
An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.