Partitioned CMP Model for Run-to-Run Control
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Solution Overview
Problem
Conventional chemical mechanical planarization (CMP) methods fail to accurately account for multiple tool and process parameters, leading to inconsistent polish rates and increased cycle times and costs due to the need for frequent qualification of CMP tools and look-ahead wafers, especially when processing new devices with varying pattern densities.
Innovation Solution
A partitioned CMP model that separates common and device-specific information, using a cumulative sum (CUSUM) methodology for tuning, allows for accurate polish time determination and adaptive control of the CMP process by accounting for consumable life and pattern density, eliminating the need for pilot wafers and reducing qualification activities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMP control methods are used, then the process can handle multiple tool and process parameters, but the polish rate accuracy deteriorates due to non-linear changes with consumable life and tool variations
Solution Approach 1:
The patent implements dynamic adjustment of polish time based on real-time monitoring of consumable life and tool parameters. The system continuously updates the partitioned CMP model with current consumable age data and adjusts polish time predictions accordingly, transforming the static conventional approach into a dynamic adaptive system that maintains accuracy despite varying conditions
Solution Approach 2:
The patent changes the parameters used in polish time prediction by incorporating consumable life as a explicit variable and using partitioned modeling that separates tool-specific parameters from process parameters. This parameter transformation allows the system to account for non-linear polish rate changes while maintaining model simplicity and accuracy
2Reliability
If pilot wafers are run for each dielectric film change, then the CMP tool can be qualified, but the cycle time increases
Solution Approach 1:
The patent uses a partitioned CMP model that creates a virtual representation of the polishing process based on historical data and theoretical relationships. This model copy allows prediction of polish times for new dielectric films without physical experimentation, replacing the need for actual pilot wafer runs while maintaining qualification reliability
Solution Approach 2:
The patent performs preliminary modeling and calibration work in advance to establish the partitioned CMP model parameters. Once the model is established, it can predict polish times for any dielectric film without requiring additional pilot runs, effectively performing the qualification work beforehand
3Measurement precision
If look-ahead wafers are used for each new product device, then the device-specific polish rate can be set, but the cycle time and cost increase
Solution Approach 1:
The patent implements feedback mechanisms where actual polish results from production wafers are measured and used to refine the partitioned CMP model predictions. This feedback loop allows the system to learn device-specific characteristics from real data rather than requiring separate look-ahead wafers for calibration, maintaining precision while reducing cycle time
Solution Approach 2:
The patent creates a universal partitioned CMP model that can handle multiple device types and dielectric films with a single unified framework. The model adapts to device-specific characteristics through its parameter structure without requiring separate qualification processes for each device, making the system both precise and efficient
4Productivity
If conventional CMP methods are used, then the process can operate, but manufacturing precision deteriorates due to under-polish and over-polish issues
Solution Approach 1:
The patent replaces the mechanical trial-and-error approach of conventional CMP with a computational model-based system. The partitioned CMP model uses mathematical relationships to predict optimal polish times, substituting physical experimentation with computational calculation to achieve both high productivity and precision
Data Source
AI summary
A method for fabricating an integrated circuit includes providing a partitioned chemical-mechanical planarization (CMP) model having a plurality of model parameters that include (i) device specific model parameters and (ii) at least one common parameter. (i) include a pre-CMP thickness of a film including a first material on an in-process device, a post-CMP target thickness for the film on the in-process device, and device group properties that account for device structure for the in-process device. (ii) includes a polish rate from an unpatterned pilot wafer having a second material thereon. The second material need not be the same as the first material. The polish time is automatically determined using the partitioned CMP model. A CMP process is performed on a patterned product wafer having a plurality of the in-process devices using a recipe including the polish time.