Modular ECC Circuitry for Reconfigurable IO Routing Congestion
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Solution Overview
Problem
High-bandwidth semiconductor chips with reconfigurable logic face challenges in timely error detection and handling due to limitations in existing error handling schemes, particularly with long wire routings and routing congestions in modular Error Correction Code (ECC) implementations.
Innovation Solution
A modular ECC scheme is implemented by deploying ECC encoders and decoders close to reconfigurable components outside the FPGA, reducing wire routing congestion and routing issues through matrix partitioning, allowing local ECC computations and convergence of only parity bits for final ECC computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC encoders and decoders are deployed inside the FPGA, then error handling is provided, but wire routing congestion and routing issues occur
Solution Approach 1:
The patent divides the error handling function into two segments: modular ECC logic circuits deployed outside the FPGA and a smaller convergence function deployed inside the FPGA. This segmentation reduces wire routing congestion by placing the bulk of ECC computation closer to the reconfigurable components, while only convergence logic remains inside the FPGA.
Solution Approach 2:
The patent introduces an intermediary modular ECC logic circuit that performs preliminary error correction computations outside the FPGA. This intermediary handles most ECC operations locally, reducing the burden on internal FPGA routing and allowing only final convergence operations to occur within the FPGA boundaries.
2Device complexity
If modular ECC logic circuits are deployed outside the FPGA, then wire routing congestion is reduced, but error handling efficiency may be compromised
Solution Approach 1:
The patent merges the modular ECC logic circuits outside the FPGA with the convergence function inside the FPGA into a unified error handling system. The external modular circuits perform initial ECC computations and pass intermediate results to the internal convergence logic, which completes the error correction process, achieving both routing reduction and maintained efficiency.
Solution Approach 2:
The patent implements preliminary ECC computations in the modular logic circuits deployed outside the FPGA before data enters the FPGA. This preliminary action performs the bulk of error correction work in advance, reducing the computational burden on the FPGA and maintaining overall error handling efficiency while minimizing internal routing requirements.
3Adaptability or versatility
If reconfigurable logic is used, then adaptability to new applications is improved, but compatibility with existing error handling schemes is lost
Solution Approach 1:
The patent designs the modular ECC logic circuits with universal functionality that can adapt to different reconfiguration scenarios while maintaining standardized error handling interfaces. The modular architecture allows the same basic ECC logic to serve multiple reconfigurable logic configurations, ensuring compatibility across different applications and reconfiguration states.
Solution Approach 2:
The patent implements dynamic error handling where the modular ECC logic circuits can be reconfigured along with the main logic. This dynamic approach allows the error handling scheme to adapt to new applications while maintaining compatibility through standardized interfaces and protocols that remain consistent even as the underlying logic changes.
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AI summary
A modular Error Correction Code (ECC) scheme in a multi-channel 10 link of an integrated circuit device is provided. The integrated circuit device may include core logic circuitry that may be configured after manufacturing. To accommodate the resulting variation, the modular ECC scheme may allow for partitioning a parity check matrix associated with the configuration of the core logic and peripheries coupled to the core logic. The parity check matrix is partitioned into smaller block matrices that is programmable. Multiple ECC modules corresponding to the block matrices are used to provide error detection and correction in the multi-channel IO link. The modular ECC scheme combined with programmable matrices (configurability) enables multi-channel IO link to be flexible to form different IO topologies.