Partitioned Erase for NAND Flash Memory Capacitive Coupling
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Solution Overview
Problem
Traditional erase operations in NAND type flash memory systems lead to disparate erase rates among memory cells, resulting in over-erasure and reduced cycling life, due to capacitive coupling effects that cause uneven erase potentials across cells.
Innovation Solution
A method that partitions memory cells into subsets and applies erase voltage pulses under specific bias conditions to normalize the erase behavior of each subset, ensuring consistent erase rates by managing the voltage conditions of adjacent transistors and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional erase operations are applied to NAND flash memory, then erase speed is improved, but erase uniformity deteriorates due to capacitive coupling effects causing disparate erase rates among memory cells
Solution Approach 1:
The memory cells are divided into multiple subsets (first subset and second subset) that are erased in separate operations. This segmentation allows independent control of erase operations for different cell groups, enabling uniform erase rates across all cells despite capacitive coupling effects by erasing each subset with optimized voltage conditions specific to its position in the NAND string.
2Reliability
If high erase voltage is applied to all memory cells simultaneously, then erase completeness is improved, but over-erasure occurs in some cells reducing cycling life
Solution Approach 1:
Different voltage conditions are applied to different subsets of memory cells based on their local characteristics and positions in the NAND string. The first subset receives voltage conditions optimized for its location, while the second subset receives different voltage conditions suited to its position, ensuring each cell group achieves complete erasure without over-erasure that would reduce cycling life.
Solution Approach 2:
The erase operation is performed in periodic phases, alternating between erasing the first subset and erasing the second subset. This periodic action allows controlled, staged erasure that ensures completeness while preventing over-erasure by resetting voltage conditions between phases and allowing verification between erasure cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures more uniform erase rates across all memory cells, reducing over-erasure and extending the cycling life of NAND strings by minimizing the impact of capacitive coupling effects.
Implementation Method 1
capacitive coupling effects that cause uneven erase potentials across cells
Data Source
AI summary
A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. A second erase voltage pulse can then be applied with the second group biased for erase and the first group biased to inhibit erase. The groups are chosen so that the erase potentials for the cells in the first subset during the first pulse are about equal, so that the erase potentials for the cells in the second subset during the second pulse are about equal, and so that the erase potentials for the cells of the first subset are about the same as the erase potentials for the cells of the second subset. In one embodiment, the bias conditions for the string during each individual erase are selected so that every memory cell of the set will experience similar capacitive coupling effects from neighboring transistors.