Partitioned Erase Verification in Non-Volatile Memory
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Solution Overview
Problem
Traditional erase operations in NAND type flash memory systems result in inconsistent erase rates among memory cells, leading to over-erasure and reduced cycling life, as well as disparate threshold voltages, which can affect programming and data storage reliability.
Innovation Solution
The method involves applying erase voltage to subsets of memory cells under specific voltage conditions to normalize the erase behavior, ensuring consistent erase rates by managing the bias conditions for neighboring transistors, allowing one subset to be erased while inhibiting another, and repeating the process until all subsets are verified as erased.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional erase operations are applied to all memory cells simultaneously, then the erase process is completed quickly, but inconsistent erase rates occur among memory cells leading to over-erasure and reduced cycling life
Solution Approach 1:
The patent divides the memory cell array into multiple subsets and erases them sequentially rather than simultaneously. During each erase phase, only a selected subset of memory cells is actively erased while other subsets are inhibited, allowing different erase conditions to be applied to different groups. This segmentation resolves the contradiction by enabling controlled, uniform erase rates across all cells while maintaining overall erase efficiency.
2Reliability
If high erase voltage is applied to ensure complete erasure of all memory cells, then erasure completeness is achieved, but disparate threshold voltages occur affecting programming reliability
Solution Approach 1:
The patent applies different voltage conditions to different subsets of memory cells during the erase process. Each subset receives tailored erase conditions appropriate to its specific state and characteristics, rather than applying a uniform high voltage to all cells. This local quality approach ensures complete erasure of each cell type while maintaining uniform threshold voltage distribution across the entire array.
Solution Approach 2:
The patent incorporates verification steps after erase operations to check whether memory cells have reached the desired erased state. Based on verification results, the erase process is adjusted - continuing for subsets that need more erasure and stopping for subsets that are sufficiently erased. This feedback mechanism ensures complete erasure while preventing over-erasure and threshold voltage disparity.
3Measurement precision
If erase verification is performed on all memory cells, then erasure accuracy is ensured, but the process time increases significantly
Solution Approach 1:
The patent divides the verification process into multiple phases corresponding to the segmented erase operations. Instead of verifying all memory cells after a single comprehensive erase operation, verification is performed on each subset after its corresponding erase phase. This segmentation reduces total verification time while maintaining accuracy, as each subset is verified under appropriate conditions rather than requiring a single lengthy global verification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures more uniform erase behavior across memory cells, reducing the risk of over-erasure and extending the cycling life of memory cells by maintaining consistent threshold voltages, thereby improving data storage reliability and efficiency.
Implementation Method 1
Capacitive charge coupling between a floating gate of a memory cell and control gates of neighboring memory cells may affect the erase potential for the memory cell
Data Source
AI summary
A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. A second erase voltage pulse can then be applied with the second group biased for erase and the first group biased to inhibit erase. The groups are chosen so that the erase potentials for the cells in the first subset during the first pulse are about equal, so that the erase potentials for the cells in the second subset during the second pulse are about equal, and so that the erase potentials for the cells of the first subset are about the same as the erase potentials for the cells of the second subset. In one embodiment, the bias conditions for the string during each individual erase are selected so that every memory cell of the set will experience similar capacitive coupling effects from neighboring transistors.