Partitioned Error Code Circuit for High-Bandwidth CRC Processing
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Solution Overview
Problem
High-bandwidth cyclic redundancy check (CRC) calculations in digital networks are inefficient due to serial computation methods, requiring unfeasibly high clock rates, and existing parallel computation methods struggle with odd numbers of words or separate error calculations for distinct data messages.
Innovation Solution
A circuit with interconnected XOR gates, or an XOR tree, performs parallel error code calculations for multiple words, selectively accumulating error codes based on control signals to handle varying data message sizes and word associations, allowing for efficient error code generation and output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If serial computation methods are used for CRC calculations, then device complexity is reduced, but processing speed becomes unfeasibly slow for high-bandwidth applications
Solution Approach 1:
The error code computation is divided into multiple parallel computation units, each handling a portion of the data words. This segmentation enables simultaneous processing of multiple words, dramatically increasing throughput while keeping individual computation units relatively simple in structure
Solution Approach 2:
The patent transitions from serial (one-dimensional) processing to parallel (multi-dimensional) processing by introducing multiple computation units operating simultaneously. This dimensional change in processing architecture enables high-bandwidth handling without requiring excessively complex individual units
2Adaptability or versatility
If parallel computation methods are used for error codes, then processing speed increases, but handling odd numbers of words or separate data messages becomes difficult
Solution Approach 1:
The control circuit dynamically configures the operation of computation units based on the number of words and message boundaries. This dynamic adaptability allows the same parallel architecture to efficiently handle both odd and even numbers of words, as well as multiple separate data messages, without requiring duplicate hardware
Solution Approach 2:
The control circuit is designed to universally handle various data configurations (odd/even word counts, single/multiple messages) using the same parallel computation units. This multi-functionality eliminates the need for separate error calculation paths while maintaining processing efficiency
3Reliability
If separate error calculations are performed for each data message, then accuracy is maintained, but hardware duplication increases
Solution Approach 1:
Multiple computation units are merged into a single parallel processing system under unified control. This merging maintains separate error calculations for each data message (preserving accuracy) while sharing common control logic and accumulation resources (reducing hardware duplication)
Data Source
AI summary
A circuit provides parallel computation of error codes for simultaneously received words. The words received simultaneously may be portions of a common data message, or may be portions of distinct data messages. Accordingly, the circuit selectively accumulates the error codes based on their association with successive data words, outputting an accumulated error code when the last word of a data message has been received and the respective error code is calculated. Based on such information, the error codes calculated in parallel can be output independently, accumulated with one another, or accumulated with the error codes of a previous or subsequent calculation cycle. Thus, the circuit dynamically provides a single parallel error code generation of a given width or multiple parallel error code generations, each of a width divisible by the given width.