Partitioned Flash Translation Layer for Variable Data Storage

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Solution Overview

Problem

Conventional solid-state drives face storage efficiency issues due to fixed page sizes in nonvolatile memory, which are not adaptable to variable user data sizes, leading to hardware-intensive architectures and inefficient data extraction processes.

Innovation Solution

A partitioned flash transition layer is introduced, allowing for variable-sized data storage by compressing data, storing it in nonvolatile memory, and returning a handle for efficient data retrieval, enabling support for a wide range of data sizes and operating with non-block based data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional solid-state drives use fixed page sizes in nonvolatile memory, then the hardware architecture is simple, but storage efficiency deteriorates when user data size or usable size of each page is not fixed

Engineering Contradiction:
Improvehardware architecture simplicityVSAvoidstorage efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The flash translation layer is segmented and partitioned between the host and controller. The host handles higher-level mapping operations while the controller manages lower-level physical address translation and data storage. This segmentation allows the system to achieve variable size data storage efficiency without requiring complex hardware modifications, as the partitioned software/firmware layer handles the complexity of adapting to different data sizes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes the parameter of data size flexibility by implementing variable size data storage through the partitioned flash translation layer. Instead of being constrained by fixed page sizes, the system can accommodate different user data sizes by managing physical address mappings dynamically, thereby improving storage efficiency without fundamentally changing the hardware architecture.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If variable size flash translation layers are implemented, then storage efficiency improves for variable data sizes, but device complexity and hardware intensity increase

Engineering Contradiction:
Improvestorage efficiencyVSAvoidhardware intensity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces complex hardware-intensive variable size flash translation layers with a partitioned software/firmware approach. The flash translation layer is implemented as a partitioned system between host software and controller firmware, which manages variable size data storage through address mapping and compression algorithms rather than requiring complex hardware circuits. This substitution maintains storage efficiency while significantly reducing hardware complexity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The partitioned flash translation layer acts as an intermediary between the host and the nonvolatile memory. It receives variable size data from the host, compresses it, determines physical addresses, and manages the storage process. This intermediary layer handles the complexity of variable size data management, allowing the hardware to remain simpler while achieving high storage efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If page headers are used to identify user data storage locations, then data extraction can locate variable size data, but the data extraction process becomes more complex and time-consuming

Engineering Contradiction:
Improvevariable size data supportVSAvoiddata extraction time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The partitioned flash translation layer performs preliminary actions by pre-computing and maintaining physical address mappings for variable size data blocks. Instead of parsing page headers during data extraction, the system has already established the mapping relationships between logical and physical addresses. This preliminary action allows for faster data extraction, as the system can directly access the correct physical locations without time-consuming header parsing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where the flash translation layer continuously updates physical address mappings based on data storage operations. This feedback allows the system to maintain accurate and efficient address translations, enabling rapid data extraction without re-parsing headers. The feedback loop ensures that the mapping information remains current and accessible for quick retrieval operations.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9329991B2Translation layer partitioned between host and controller
Publication Date: 2016.05.03 SEAGATE TECH LLC
  • US9329991B2 patent drawing
  • US9329991B2 patent drawing
  • US9329991B2 patent drawing

AI summary

A method for using a partitioned flash transition layer is disclosed. Step (A) receives, at an apparatus from a host, a write command having first write data. Step (B) generates second write data by compressing the first write data in the apparatus. The second write data generally has a variable size. Step (C) stores the second write data at a physical location in a nonvolatile memory. The physical location is a next unwritten location. Step (D) returns, from the apparatus to the host in response to the write command, an indication of the physical location.