Partitioned Garbled Circuits for Multi-Variable Zero-Knowledge Proofs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing zero-knowledge proof technologies are limited to monolithic states, requiring multiple iterations for polynomial equation solutions, leading to high computational overhead and inability to handle multiple variables efficiently.
Innovation Solution
A method involving polylithic syntax decomposition and partitioned garbled circuits allows multiple verifiers to jointly compute a digest of a garbled circuit, enabling verification of multiple variables without revealing their true values, using non-interactive oblivious transfer and multiparty verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing zero knowledge technologies are used with monolithic state, then the proof system can handle single variable verification, but computational overhead is significantly large and multiple iterations are required
Solution Approach 1:
The patent divides the monolithic garbled circuit into multiple partitioned garbled circuits, where each partition handles a specific variable or subset of variables. This segmentation allows parallel processing of multiple variables simultaneously, eliminating the need for multiple sequential iterations and significantly reducing computational overhead while maintaining verification accuracy.
2Adaptability or versatility
If existing zero knowledge technologies are used with monolithic state, then the proof system can verify statements, but it cannot efficiently handle multiple variables at once
Solution Approach 1:
The system partitions the verification process into multiple independent garbled circuit portions, each handling specific variables. This segmentation enables the system to efficiently handle multiple variables simultaneously while keeping each partition's complexity manageable, thus improving adaptability without proportionally increasing overall system complexity.
Solution Approach 2:
The patent combines multiple partitioned garbled circuits into a unified verification framework where all partitions work together to verify the complete statement. This merging approach allows the system to handle multiple variables in a single verification process, enhancing versatility while maintaining structured complexity through the modular partition architecture.
3Reliability
If multiple iterations are performed to achieve small soundness error, then verification accuracy is improved, but computational overhead increases significantly
Solution Approach 1:
By segmenting the verification into partitioned garbled circuits that process multiple variables in parallel, the system achieves the required soundness error in a single iteration rather than requiring multiple sequential iterations. This segmentation maintains verification accuracy while dramatically reducing computational overhead and energy consumption.
Data Source
AI summary
A method, apparatus and system for implementing zero-knowledge proofs is provided. Partitioned garbled circuits are used to achieve a joint zero-knowledge proof system with full syntax verification. A polylithic syntax is used for handling complex semantics involving more than one statement to be proved and verified. Multiple verifiers can participate in a coordinated manner to perform the verification. Different verifiers can perform different parts of the verification.