Partitioned Graphics Memory Non-Power-of-Two Address Translation
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Solution Overview
Problem
Conventional partitioned graphics memories are limited to a power of two number of partitions and DRAMs, which increases costs and reduces yield due to larger chip areas, and does not support arbitrary numbers of partitions.
Innovation Solution
A graphics system with a partitioned graphics memory that supports a non-power of two number of operative memory elements, where each partition includes dynamic random access memories (DRAMs) and a graphics processing unit performs memory address translation to map physical memory addresses to individual partitions, allowing for a flexible number of partitions and sub-partitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional partitioned graphics memories use a power of two number of partitions and DRAMs, then the system follows standard binary address space scaling, but the chip area increases and manufacturing yield decreases
Solution Approach 1:
The patent implements dynamic partitioning where the number of active partitions can be configured at runtime rather than being fixed at power-of-two values. The memory controller dynamically adjusts the number of partitions based on actual memory bandwidth requirements, allowing the system to adapt between 1 to N partitions where N is not necessarily a power of two. This dynamic configuration reduces chip area by activating only the necessary number of partitions while maintaining the ability to scale up when needed.
Solution Approach 2:
The system changes the parameter of partition count from fixed power-of-two values to variable non-power-of-two values. By allowing the partition count to be any integer between 1 and N, the system can optimize memory bandwidth utilization without being constrained by binary scaling requirements. This parameter change enables precise matching of memory capacity to actual workload demands, reducing unnecessary chip area.
2Quantity of substance
If the number of DRAMs is increased to double memory size in successive product generations, then memory capacity increases, but costs increase and yield decreases due to larger chip area
Solution Approach 1:
The patent segments the memory system into multiple independent partitions, each capable of being independently configured and activated. Instead of using a single large DRAM array that requires full chip area, the system divides memory into N partitions where only the necessary number are activated based on capacity requirements. This segmentation allows flexible memory capacity scaling without proportionally increasing chip area, as unused partition areas can be left inactive or repurposed.
Solution Approach 2:
The memory controller is designed with universal addressing logic that can handle any number of partitions from 1 to N, making the same hardware infrastructure adaptable to different memory capacity requirements. This multi-functionality allows a single chip design to serve multiple market segments with different capacity needs without requiring separate optimized designs for each capacity level, thereby improving manufacturing yield.
3Ease of manufacture
If conventional systems use power of two number of partitions, then binary address space scaling is simplified, but arbitrary numbers of partitions cannot be supported
Solution Approach 1:
The patent introduces an intermediary address translation layer between the logical address space and physical memory locations. The memory controller includes translation logic that converts logical addresses into physical addresses across non-power-of-two partitions. This intermediary translation mechanism handles the complexity of arbitrary partition mapping, allowing the system to support any number of partitions while maintaining simplified address generation at the application level. The translation layer acts as a mediator that absorbs the mapping complexity.
Solution Approach 2:
The system adds a dimension of configurability to the partition structure by introducing runtime configuration capabilities. Instead of fixing the partition structure at compile time or at power-of-two values, the system adds a configuration dimension that allows dynamic adjustment of partition counts. This additional dimension enables the system to support arbitrary partition numbers while maintaining backward compatibility with traditional address space conventions.
Data Source
AI summary
A graphics system has a partitioned graphics memory that includes memory elements. The system supports having an non-power of two number of active memory elements. In one implementation, the memory elements are dynamic random access memories (DRAMs) and the system supports having a non-power of two number of active DRAMs.