Partitioned Graphics Memory Tag Addressing for Non-Power-of-Two Configurations
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Solution Overview
Problem
Conventional partitioned graphics memories are limited to a power of two number of partitions, which increases costs and reduces yield due to the need for larger chip areas when doubling the number of DRAMs in successive product generations, and do not efficiently support arbitrary numbers of partitions.
Innovation Solution
A graphics system utilizing a virtual memory and page table entries for address mapping, allowing for both power-of-two and non-power-of-two numbers of partitions, with a memory controller capable of interfacing a non-power-of-two number of DRAMs and sub-partitions, and a tag RAM to store compression tags, enabling efficient address translation and data access across multiple partitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of partitions is doubled to increase memory size, then the effective memory capacity is improved, but the chip area increases and manufacturing yield decreases
Solution Approach 1:
The graphics memory is divided into multiple partitions, each with its own data bus and sub-partitions. This segmentation allows the memory system to achieve large effective capacity through multiple smaller units rather than one large chip, thereby improving yield while maintaining scalability.
Solution Approach 2:
The patent introduces a multi-dimensional memory architecture with partitions, sub-partitions, and data buses operating at different levels. This dimensional organization allows efficient addressing and access patterns that reduce the physical area required while maintaining large effective memory capacity.
2Ease of operation
If conventional power-of-two partitioning is used, then the memory addressing is simplified, but the flexibility to support arbitrary partition numbers is limited
Solution Approach 1:
The memory controller implements dynamic partition assignment where partitions can be selectively enabled or disabled based on configuration. The address routing module dynamically maps logical addresses to physical partition locations, allowing the system to adapt to different partition configurations while maintaining efficient addressing through programmable control logic.
Solution Approach 2:
The system allows configuration parameters such as the number of partitions, data bus width, and sub-partition arrangement to be changed without redesigning the fundamental architecture. This parameter flexibility enables the same hardware to support various partition schemes from 2 to 64 partitions while maintaining addressing efficiency.
Data Source
AI summary
A graphics system has virtual memory and a partitioned graphics memory that supports having an non-power of two number of dynamic random access memories (DRAMs). The graphics system utilizes page table entries to support addressing Tag RAMs used to store tag bits indicative of a compression status.