Logically Partitioned Memory Array for Queue Management
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Solution Overview
Problem
Existing memory queue technologies face challenges in efficiently managing data storage and retrieval in synchronous and asynchronous environments, particularly in handling invalid data and partitioning memory arrays for optimal performance.
Innovation Solution
The implementation of multiple first in, first out (FIFO) and first in, random out (FIRO) memory queues with logically partitioned memory arrays and control logic that manages read and write pointers, status flags, and handshaking signals to facilitate efficient data access and storage across multiple memory sub-arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory arrays are partitioned into multiple sub-arrays with independent read/write pointers, then data storage and retrieval efficiency is improved, but device complexity increases
Solution Approach 1:
The memory array is divided into multiple independently accessible sub-arrays, each with its own read pointer and write pointer. This segmentation allows parallel read/write operations to occur simultaneously in different sub-arrays, improving throughput and efficiency while the modular structure helps manage complexity through clear separation of functions.
Solution Approach 2:
The control logic is designed to universally manage multiple sub-arrays using the same read/write pointer mechanisms and status flag systems. This multi-functional approach allows a single control unit to handle various operations across different sub-arrays without requiring separate dedicated control logic for each, thereby improving efficiency while controlling complexity growth.
2Reliability
If status flags are used to mark invalid data in memory columns, then data integrity is improved, but device complexity increases
Solution Approach 1:
Status flags are implemented to provide feedback about the validity of data in each memory column. When data is written or read, the corresponding status flag is updated to reflect the current state (valid/invalid). This feedback mechanism ensures data integrity by allowing the system to track and respond to the state of each memory location, preventing errors while maintaining relatively simple flag-based implementation.
3Productivity
If sequential read operations are performed from top entry to bottom entry in memory columns, then data access efficiency is improved, but loss of time occurs due to invalid data skipping
Solution Approach 1:
The status flags are set in advance to indicate which memory columns contain valid or invalid data before read operations begin. This preliminary marking allows the control logic to quickly identify and skip invalid columns during sequential reads, avoiding unnecessary access attempts and reducing the time lost to invalid data without compromising the overall sequential access efficiency.
Data Source
AI summary
Memory queues described herein use a single hardware and/or software architecture for a memory array. This memory array can be partitioned to be between one memory sub-array to implement a single memory queue and multiple memory sub-arrays to implement multiple memory queues. Various electrical signals provided by or provided to these multiple memory queues include addressing information to associate these various control signals with one or more of the multiple memory sub-arrays. In some situations, the memory queues can externally associate their corresponding read pointers to entries of one of their memory sub-arrays. In these situations, these memory queues can dynamically associate their read pointers to point to any entry from among their memory arrays and to read the data store therein starting from any random entry within their memory arrays.