Partitioned Memory Calibration for IR Drop Reduction

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In-memory processing systems face challenges with increased complexity due to large memory cell arrays, leading to local voltage drops and processing errors, particularly in neural networks where multiply-and-accumulate operations dominate.

Innovation Solution

A partitioned memory architecture with single or dual resistor memory elements, incorporating programmable resistors and additional circuitry for in-memory pipeline processing with minimal local IR drops, enabling calibration processing through feedback buffers and multiplexors that connect programmable resistors to either operational or calibration circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If large memory cell arrays are used to implement complex neural networks, then processing capability is improved, but local voltage drops increase leading to processing errors

Engineering Contradiction:

Improveprocessing capabilityVSAvoidprocessing accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The memory array is divided into multiple memory banks, each handling a portion of the neural network computation. This segmentation reduces the size of individual arrays, thereby minimizing local voltage drops while maintaining overall processing capability through parallel operation of multiple banks.

Inventive Principle:

Principle #1Segmentation

2Reliability

If memory arrays are partitioned into multiple banks, then local IR drops are reduced, but device complexity increases due to additional calibration circuitry

Engineering Contradiction:

Improvevoltage stabilityVSAvoidcircuit architecture

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The calibration circuitry is merged with the operational memory banks, sharing common bitlines and sensing elements. This integration reduces the overall device complexity compared to having separate calibration and operational arrays, while still enabling accurate compensation for IR drops through calibration processing.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The memory banks are designed to serve dual purposes: operational processing and calibration processing. The same bitlines and sensing elements are used for both functions, eliminating the need for dedicated calibration hardware and reducing overall system complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Measurement precision

If calibration processing is performed separately from operational processing, then measurement precision is improved, but productivity decreases due to processing pauses

Engineering Contradiction:

Improveresistance measurement accuracyVSAvoidprocessing throughput

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The system enables continuous processing by allowing calibration operations to be performed on one memory bank while other banks continue operational processing. The pipeline architecture ensures that calibration does not halt overall system throughput, maintaining productivity while achieving measurement precision.

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

Calibration is performed preliminarily during idle periods or between operational phases, preparing the memory banks for accurate computation without interrupting the main processing workflow. This timing strategy ensures measurement precision is achieved while minimizing impact on overall productivity.

Inventive Principle:

Principle #10Preliminary action

4Measurement precision

If duplicate pairs of memory elements are used for concurrent calibration, then calibration precision is improved, but device complexity increases

Engineering Contradiction:

Improvecalibration accuracyVSAvoidmemory element structure

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

Instead of adding duplicate memory elements for calibration, the system inverts the approach by using the same memory elements for both operational and calibration functions at different times. This inversion reduces device complexity while maintaining calibration precision through proper timing and control of the dual-mode operation.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS12136468B2Calibration methods and structures for partitioned memory architecture with single resistor or dual resistor memory elements

Publication Date: 2024.11.05 GLOBALFOUNDRIES US INC

AI summary

Disclosed structures include a partitioned memory architecture, which includes single resistor or dual resistor memory elements, which is configured for in-memory pipeline processing with minimal local IR drops, and which further includes additional circuitry to facilitate calibration processing. In some embodiments, the additional circuitry enables calibration processing when in-memory pipeline processing is paused. In these embodiments, the same bitlines and data sensing elements used for in-memory pipeline processing are also used for calibration processing. In other embodiments, the additional circuitry enables calibration processing concurrent with in-memory pipeline processing. In these embodiments, the additional circuitry includes duplicate pairs of memory elements with programmable resistors that can be connected to the operational circuitry for in-memory pipeline processing, to the calibration circuitry (including calibration-specific sense lines and sensing elements) for calibration processing, or to neither such that one memory element of the duplicate pair always remains operational allowing the other to undergo calibration.