Partitioned Memory Circuit Cross-Matrix Calculation
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Solution Overview
Problem
Existing memory circuits face challenges in reducing access times when the number of rows in the matrix is large, and they are limited to performing calculation operations only within the same module matrix due to partitioning, which restricts data access speed and dynamic consumption.
Innovation Solution
The memory circuit is partitioned into multiple matrices with global and local read bit lines, allowing data access across different matrices and reducing access times through a connection circuit that transfers binary signals between local and global read bit lines, enabling calculation operations across different matrices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the memory circuit is partitioned into multiple matrices, then calculation operations can be performed across different matrices improving versatility, but the device complexity increases due to additional connection circuits and global read bit lines
Solution Approach 1:
The memory circuit is divided into multiple independent matrices (first matrix and second matrix), each capable of storing data and performing local calculations. This segmentation allows parallel operation of multiple matrices while maintaining modular complexity management.
Solution Approach 2:
The connection circuit and global read bit lines serve multiple functions: they connect different matrices for cross-matrix calculations, transfer data between matrices, and enable both local and global read operations. This multi-functionality reduces the need for separate dedicated circuits for each operation type.
2Speed
If global read bit lines are used to access data across different matrices, then access speed is improved, but dynamic consumption increases due to the larger signal transfer area
Solution Approach 1:
The system uses local read bit lines for matrix-internal data access and reserves global read bit lines specifically for cross-matrix access. This localized approach ensures that most operations use the lower-power local lines, while global lines are activated only when necessary for inter-matrix operations.
Solution Approach 2:
The connection circuit acts as an intermediary between matrices, transferring signals through controlled paths. It enables selective activation of global read bit lines only when cross-matrix access is required, rather than continuously activating all bit lines, thereby reducing overall dynamic consumption.
3Productivity
If multiple rows are simultaneously selected for reading, then calculation operations can be performed in-situ improving productivity, but the access time increases due to the larger number of rows to be accessed
Solution Approach 1:
By dividing the memory into multiple matrices, the system can simultaneously select and read multiple rows across different matrices in parallel. Each matrix can independently perform row selection and reading operations, effectively increasing throughput without proportionally increasing the access time for each individual matrix.
Data Source
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AI summary
The invention relates to a memory circuit comprising a plurality of elementary cells (10) distributed into several matrices (A1, A2), each comprising N columns, with N an integer greater than or equal to 2, wherein: each column of each matrix comprises a local first row of bits (LRBL) <j>) directly connected to each of the cells in the column; each column of each matrix includes a global first bit row (GRBL <j>) connected to the first local bit line (LRBL <j>) of the column by a first link circuit (31); and the first global bit lines (GRBL <j>) columns of the same rank j of the different matrices (A1, A2), with j an integer ranging from 0 to M-1, are linked together.</j> </j> </j> </j>