Partitioned Memory Architecture for In-Memory Pipeline Processing
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Solution Overview
Problem
In-memory processing systems face challenges with increasing array size leading to local voltage drops, resulting in processing errors due to the complexity of neural networks used in applications like image and audio processing.
Innovation Solution
A partitioned memory architecture with single or dual resistor memory elements, arranged in rows and columns, incorporating track-and-hold devices, amplifiers, and feedback buffer circuits to minimize local IR drops and enable pipeline processing without data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the memory array size is increased to implement more complex neural networks, then the processing capability and neural network complexity increase, but the local voltage drops increase leading to processing errors
Solution Approach 1:
The memory array is divided into multiple memory banks, each processing a subset of neural network computations independently. This segmentation allows larger overall array capacity while maintaining smaller individual bank sizes that avoid voltage drop issues, thus resolving the contradiction between neural network complexity and processing accuracy.
Solution Approach 2:
Feedback buffer circuits are introduced as intermediary components between memory banks to capture and hold intermediate computation results. These buffers prevent voltage drop-induced errors from propagating through the system, maintaining processing accuracy while enabling larger memory arrays for complex neural networks.
2Productivity
If the memory array size is increased to implement more complex neural networks, then the processing capability increases, but voltage drops lead to processing errors
Solution Approach 1:
The memory array is divided into multiple memory banks, each processing a subset of neural network computations independently. This segmentation allows larger overall array capacity while maintaining smaller individual bank sizes that avoid voltage drop issues, thus resolving the contradiction between neural network complexity and processing accuracy.
Solution Approach 2:
Feedback buffer circuits are introduced as intermediary components between memory banks to capture and hold intermediate computation results. These buffers prevent voltage drop-induced errors from propagating through the system, maintaining processing accuracy while enabling larger memory arrays for complex neural networks.
3Reliability
If feedback buffer circuits are added to minimize voltage drop effects, then processing accuracy is maintained, but device complexity increases
Solution Approach 1:
The feedback buffer circuit functionality is merged with the existing memory bank structure, combining the buffer operations with the memory access logic. This integration reduces the additional circuit complexity while maintaining the voltage drop compensation benefits, thus resolving the contradiction between processing accuracy and device complexity.
4Reliability
If track-and-hold devices and amplifiers are added to each memory bank, then voltage stability is improved, but device complexity increases
Solution Approach 1:
The track-and-hold devices and amplifiers are merged with the memory bank structure, integrating voltage stabilization functions into the existing memory access logic. This integration reduces the additional circuit complexity while maintaining the voltage stability benefits, thus resolving the contradiction between processing accuracy and device complexity.
Data Source
AI summary
A structure for in-memory pipeline processing includes a memory bank array. Each bank includes single resistor or dual resistor memory elements connected between input nodes, respectively, and bitline(s) (e.g., a single bitline for a single resistor memory element and first and second bitlines for a dual resistor memory element). A feedback buffer is connected to each bitline and a corresponding output node in each bank and a column interconnect line connects corresponding output nodes of all banks in the same column. The initial bank in each row includes amplifiers connected between the input nodes and memory elements and track-and-hold devices (THs) connected to the input nodes to facilitate pipeline processing. Outputs of the amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks.