Partitioned Memory Data Path Layout for Lower RC Delay
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Solution Overview
Problem
Existing memory architectures face challenges in reducing capacitance and gate delay, leading to increased power consumption and access time, particularly in lower technology nodes, due to large capacitive loads and resistance in data paths.
Innovation Solution
A memory architecture with a multi-stage data path-partitioning scheme that strategically places write assist circuits and charge pumps, reducing global bit-line lengths and capacitance, and optimizing RC delay through careful placement of decoder and control circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If buffers are inserted into clock paths to reduce RC delay, then access time is improved, but silicon area and gate delay increase
Solution Approach 1:
The patent divides the memory into multiple banks (first bank, second bank, third bank, fourth bank) and implements separate clock paths for each bank. This segmentation allows independent optimization of each bank's clock distribution, reducing the overall RC delay without requiring buffers across the entire memory array, thus improving access time while minimizing silicon area usage.
2Speed
If buffers are inserted into clock paths to reduce RC delay, then access time is improved, but gate delay increases
Solution Approach 1:
The memory is segmented into multiple banks with dedicated clock paths for each bank. By localizing clock distribution to smaller bank-level segments rather than using global buffers, the patent reduces the propagation delay through fewer buffer stages while still achieving reduced RC delay within each bank, thus improving access time without significantly increasing gate delay.
Solution Approach 2:
The patent introduces a bank-level dimension to clock distribution, creating hierarchical clock paths that operate at different levels (global clock input to banks, then bank-specific clock signals to bit cells). This dimensional approach allows clock signals to reach memory elements more directly, reducing gate delay while improving access time.
3Speed
If more input gate capacitance and metal capacitance are introduced to reduce RC delay, then access time is improved, but toggle power increases
Solution Approach 1:
The patent segments the memory into multiple banks, each with its own clock path and reduced capacitance load. By distributing the total capacitance across separate bank-level clock paths rather than using a single high-capacitance global clock path, the patent reduces the toggle power required for each individual clock signal while maintaining improved access time through reduced RC delay in each segment.
Data Source
AI summary
A memory comprising a multi stage data path-partitioning circuit, the memory comprising at least: a first data path level partitioning comprising at least one input configured to input data to or output data from the memory via at least one global input-output circuit; a second data path level partitioning configured to input data to or output data from the memory between one of a plurality of write assist circuits and one of the at least one global input-output circuit wherein at least one of the plurality of write assist circuits and at least another of the plurality of write assist circuits are located in a central portion of an upper bitcell memory array and an lower bitcell memory array respectively; a third data path level partitioning configured to input data to or output data from the memory between one of a plurality of column multiplexing circuitry and sense amplifier circuits and one of the plurality of write assist circuits.