Partitioned NVMe Controller Memory Buffer for Power Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face challenges in increasing performance and efficiency while reducing power consumption, particularly in managing host-write transactions and storing data effectively within the controller's memory space.
Innovation Solution
A controller is configured to receive and classify host-write transactions, generate parity data, and store associated data in a memory space with partitioned areas using different error correction code schemes based on the type of transaction, allowing for efficient storage and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If host-write transactions are stored in a unified memory space without partitioning, then the memory management is simpler, but the power consumption increases and operational efficiency decreases
Solution Approach 1:
The memory space in the controller is divided into multiple partitions, where each partition is associated with a specific type of data structure (e.g., submission queues, completion queues, command queues). This segmentation allows the controller to manage different types of transactions in dedicated areas, reducing power consumption by activating only the necessary partitions and improving operational efficiency through optimized error correction code schemes for each partition type.
2Reliability
If error correction code block size is increased for all transactions, then data reliability improves, but the storage efficiency and power consumption worsen
Solution Approach 1:
Different partitions of the memory space are associated with different error correction code block sizes based on the type of data structure they store. For example, partitions storing critical command queues may use larger ECC block sizes for higher reliability, while partitions storing less critical data use smaller ECC block sizes to reduce power consumption and improve storage efficiency. This local differentiation optimizes the balance between reliability and power consumption.
3Productivity
If all host-write transactions are processed with the same error correction code scheme, then the processing logic is simpler, but the operational efficiency and power consumption are suboptimal
Solution Approach 1:
The controller dynamically selects and applies different error correction code schemes based on the type of host-write transaction being processed. When a transaction is received, the controller classifies it according to its data structure type and routes it to the appropriate partition with the matching ECC scheme. This dynamic adaptation improves operational efficiency by using optimized processing paths while the classification mechanism manages the complexity of handling multiple transaction types.
Data Source
AI summary
A method of accessing a storage device, including receiving, by a controller of the storage device, a host-write transaction directed to a memory space defined within the controller. The controller then classifies the host-write transaction based on a type of the host-write transaction to generate a classified transaction, and generates parity data based on the classified transaction. The controller stores data associated with the host-write transaction and the parity data in a memory of the controller. The method includes determining a destination address of the classified transaction and classifying, based on the destination address. Generating the parity data includes determining an allocated block size associated with the destination address and generating the parity data based on the allocated block size. The allocated block size varies based on the destination address. The method additionally includes translating the host-write transaction from a first protocol to a Non-Volatile Memory Express (NVMe) protocol.