Partitioned Semiconductor Package Bonding for Precise Substrate Alignment
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Solution Overview
Problem
The increasing demand for semiconductor devices with high performance and multifunctionality leads to larger substrate sizes with more complex electrical circuitry, resulting in decreased yield and manufacturing complexity, as well as alignment issues during encapsulant filling, which affects the precise connection of substrates and electrical performance.
Innovation Solution
A semiconductor package structure comprising two partitioned substrates with conductive traces of varying line widths and spaces, electrically connected through a pad layer and a conductive bonding layer, eliminating the need for conductive pillars and improving alignment using self-alignment of solder paste during the reflow process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the substrate size is increased to install more semiconductor devices, then the device functionality is improved, but the manufacturing yield decreases and process complexity increases
Solution Approach 1:
The patent divides a large substrate into multiple smaller partitioned substrates (first substrate, second substrate, etc.). Each partitioned substrate can be manufactured independently with standard processes, maintaining high yield. The substrates are then connected side-by-side to form a larger functional package, achieving the desired device functionality without sacrificing manufacturing yield.
2Adaptability or versatility
If the substrate size is increased to install more semiconductor devices, then the device functionality is improved, but the manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into independent stages: manufacturing individual partitioned substrates using standard processes, connecting them side-by-side on a carrier, and finally encapsulating the assembly. This segmentation allows each stage to be optimized independently, reducing overall process complexity while achieving large-scale functionality.
Solution Approach 2:
A carrier is introduced as an intermediary structure to hold multiple partitioned substrates during the connection and encapsulation processes. The carrier provides a standardized platform for assembly, simplifying the manufacturing process by decoupling the substrate connection step from the encapsulation step and enabling precise alignment.
3Reliability
If conductive pillars are used to connect substrates, then electrical connection is achieved, but alignment precision deteriorates during encapsulant filling
Solution Approach 1:
The patent removes the conductive pillars from the connection structure and replaces them with a pad layer and conductive bonding layer formed directly on the substrate surfaces. This extraction eliminates the alignment precision problems associated with conductive pillars during encapsulant filling, while the pad layer and bonding layer provide robust electrical connection through standardized bonding processes.
4Manufacturing precision
If solder paste self-alignment is used during reflow, then alignment precision is improved, but position shifts occur during encapsulant filling
Solution Approach 1:
The solder paste is applied to the pad layer in advance during the reflow process, establishing precise alignment between substrates before encapsulation. The preliminary bonding creates a stable connection that resists position shifts during subsequent encapsulant filling, combining the alignment benefits of solder paste self-alignment with position stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces manufacturing complexity, enhances yield, and improves electrical performance by ensuring precise substrate alignment and connection, while reducing the distance between substrates and minimizing position shifts during encapsulant filling.
Implementation Method 1
The conductive bonding layer is disposed between the pad layer and the second surfaces of the first substrate and the second substrate
Implementation Method 2
improving alignment using self-alignment of solder paste during the reflow process
Data Source
AI summary
A semiconductor package structure includes a first substrate, a second substrate, a pad layer and a conductive bonding layer. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a first surface and a second surface opposite to the first surface. The second substrate is disposed side-by-side with the first substrate. The pad layer is disposed on the second surface of the first substrate and the second surface of the second substrate. The conductive bonding layer is disposed between the pad layer and the second surfaces of the first substrate and the second substrate.