Partitioned Parallel Data Movement in Processing-in-Memory Devices
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Solution Overview
Problem
In processing-in-memory (PIM) devices, data movement between and within memory banks is sequential, leading to inefficiencies in data processing time and power consumption, as existing technologies often require external communication and do not optimize the integration of processing resources with memory arrays.
Innovation Solution
The implementation of partitioned parallel data movement within a memory device, where the memory device is divided into partitions with shared I/O lines and isolation circuitry, allowing for simultaneous data movement across multiple subarrays within each partition, reducing the need for external communication and enhancing processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data movement is performed sequentially between memory banks, then device complexity is reduced, but data processing time increases
Solution Approach 1:
The memory device is divided into multiple partitions, each capable of independent parallel data movement operations. This segmentation allows simultaneous data transfers across different partitions without requiring complex centralized control, thus reducing device complexity while improving data processing throughput
Solution Approach 2:
The patent introduces a parallel dimension to data movement by enabling simultaneous operations across multiple partitions. Instead of sequential single-dimensional data transfer, the system utilizes multi-dimensional parallelism where multiple data movements occur concurrently in different partition segments
2Use of energy by moving object
If data movement is performed sequentially between memory banks, then power consumption is reduced, but productivity decreases
Solution Approach 1:
By segmenting the memory device into independent partitions with dedicated I/O lines, each partition can perform data movement independently. This allows the system to activate only the necessary partitions for current operations, maintaining lower overall power consumption while achieving higher throughput through parallel operations in multiple active partitions
Solution Approach 2:
The system dynamically activates specific partitions based on data movement requirements. Isolation circuitry enables or disables specific partition I/O lines as needed, allowing the memory device to adapt power consumption to actual processing needs while maintaining the capability for high-throughput parallel operations when required
3Device complexity
If external communication is used for data transfer, then device complexity is reduced, but data movement time increases
Solution Approach 1:
Multiple partition I/O lines are merged into a shared external I/O interface. This allows parallel data movements from multiple partitions to be aggregated and transmitted through a single external interface, reducing the need for multiple complex external communication channels while maintaining fast parallel data movement within the device
4Productivity
If parallel data movement is enabled across multiple partitions, then productivity increases, but device complexity increases
Solution Approach 1:
The memory device is divided into independent partitions with dedicated I/O lines and isolation circuitry for each. This segmentation enables parallel operations while keeping control logic distributed and simple within each partition, avoiding the need for complex centralized control that would increase overall device complexity
Data Source
AI summary
The present disclosure includes apparatuses and methods for partitioned parallel data movement. An example apparatus includes a memory device that includes a plurality of partitions, where each partition of the plurality of partitions includes a subset of a plurality of subarrays of memory cells. The memory device also includes sensing circuitry coupled to the plurality of subarrays, the sensing circuitry including a sense amplifier. A controller for the memory device is configured to direct a first data movement within a first partition of the plurality of partitions in parallel with a second data movement within a second partition of the plurality of partitions.


