Partitioned Pipelined Delay Chains for Memory Timing Control
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Solution Overview
Problem
Conventional memory buffers face challenges in efficiently managing variable timing for multiple signals due to excessive layout area requirements and inefficiencies in supporting command-specific timing, particularly when slower signals respond to faster signals, necessitating improved control mechanisms.
Innovation Solution
A pipelined delay chain with a cascaded arrangement of primary and secondary delay chains, along with control signal sequence generators, provides programmable delays and independent control over signals with different timing requirements, utilizing serially-linked registers and first-in first-out (FIFO) buffers to manage commands and control signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional pipelines are used to delay command and control data, then the timing of signals can be controlled, but the layout area required becomes excessive
Solution Approach 1:
The delay chain is divided into multiple segments (first delay chain, second delay chain, third delay chain) that can be independently controlled. Each segment handles specific signals with different timing requirements, allowing efficient use of layout area while providing the necessary delay timing for command and control data signals.
Solution Approach 2:
The patent implements dynamically controllable delay chains where the delay amount can be adjusted based on timing requirements. Control logic selectively activates different delay chain segments and adjusts their delay parameters to match varying timing needs of different signal types, optimizing both area usage and timing control.
2Loss of time
If conventional pipelines are used for signal delay, then timing control is provided, but efficiency in supporting variable command-specific timing is reduced
Solution Approach 1:
Different delay chain segments are optimized for specific signal types and timing requirements. The first delay chain handles command signals, the second handles control data, and the third handles other control signals. Each segment has tailored delay parameters and control logic, providing efficient variable timing control for each signal category without compromising overall system productivity.
3Area of stationary object
If a single delay chain is used for all signals, then layout area is reduced, but independent control between signals with different timing requirements is lost
Solution Approach 1:
The delay control system is segmented into multiple independent delay chains, each dedicated to specific signal types. This segmentation enables independent timing control for commands, control data, and other signals while maintaining a compact layout through shared control logic and hierarchical organization of the delay segments.
Solution Approach 2:
The control logic unit serves multiple functions by managing different delay chain segments. It can selectively activate and configure each delay chain based on the required timing, providing universal control capability across all signal types while maintaining area efficiency through shared control infrastructure.
4Adaptability or versatility
If timing of faster signals is changed, then adaptability is improved, but it causes problems for slower signals that respond to faster signals
Solution Approach 1:
The delay chains are designed with dynamic control capability that allows timing of faster signals to be adjusted independently. The control logic monitors and coordinates timing changes across different signal paths, ensuring that when faster signal timing is modified, the corresponding slower response signals are appropriately synchronized to maintain reliable signal relationships.
Data Source
AI summary
A timing controller includes a pipelined delay chain configured to process commands and control signals associated with the commands between a first device and a plurality of second devices having different timing requirements. The pipelined delay chain includes a cascaded arrangement of a primary delay chain, at least one secondary delay chain and a plurality of control signal sequence generators responsive to signals generated by the at least one secondary delay chain. The primary delay chain may include a plurality of serially-linked registers configured to support a pipelining of the commands and a stack configured to support operations to push and pop the control signals associated with the commands to and from the stack.