Partitioned Platelines in Ferroelectric Memory Devices
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Solution Overview
Problem
Ferroelectric memory devices face inefficiencies in power dissipation when writing data to partial rows, as existing technologies require reading the entire row to update only a portion, leading to excessive power consumption, which is problematic for low-power applications like portable devices.
Innovation Solution
The implementation of partitioned platelines in ferroelectric memory devices, where multiple plateline groups are associated with each column and row, allowing independent access and reduced power consumption by writing only to the specific cells that need updating, rather than the entire row.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional single plateline architecture is used, then device complexity is reduced, but power dissipation increases when writing to partial rows
Solution Approach 1:
The plateline is divided into multiple independent segments (first plateline segment, second plateline segment) that can be independently controlled. This segmentation allows selective activation of only the necessary segment when writing to partial rows, reducing power dissipation by avoiding unnecessary writes to other segments. The segmentation directly addresses the technical contradiction by enabling energy efficiency while managing device complexity through modular design.
2Loss of energy
If partitioned platelines are implemented, then power dissipation is reduced, but device complexity increases
Solution Approach 1:
The plateline is divided into multiple independent segments (first plateline segment, second plateline segment) that can be independently controlled. This segmentation allows selective activation of only the necessary segment when writing to partial rows, reducing power dissipation by avoiding unnecessary writes to other segments. The segmentation directly addresses the technical contradiction by enabling energy efficiency while managing device complexity through modular design.
3Loss of energy
If entire row is read and written to update partial data, then data integrity is maintained, but power dissipation increases
Solution Approach 1:
The plateline is divided into multiple independent segments (first plateline segment, second plateline segment) that can be independently controlled. This segmentation allows selective activation of only the necessary segment when writing to partial rows, reducing power dissipation by avoiding unnecessary writes to other segments. The segmentation directly addresses the technical contradiction by enabling energy efficiency while managing device complexity through modular design.
Solution Approach 2:
Instead of reading and writing the entire row when only partial data needs updating, the invention applies partial action by activating only the specific plateline segment corresponding to the target cells. This selective approach reduces power dissipation significantly while maintaining data integrity, directly addressing the contradiction between energy efficiency and operational simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power dissipation by approximately 43% compared to prior solutions, enabling more efficient data writing to partial rows while maintaining a balanced design between power consumption and area usage.
Implementation Method 1
A ferroelectric memory device stores data and/or program code by employing ferroelectric capacitors that are constructed using ferroelectric dielectric material that may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within perovskite crystals in the ferroelectric material.
Data Source
AI summary
One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in rows and columns. A row of ferroelectric memory cells includes a common wordline that allows access to the memory cells of the row and also includes at least two platelines associated with the row. At least one of the at least two platelines is associated with adjacent columns of ferroelectric memory cells within the row. The row of ferroelectric memory cells includes another word line which is not associated with the at least two platelines. Other methods and systems are also disclosed.