Partitioned Simulation Synchronization With Backplane Time Windows
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Solution Overview
Problem
Existing systems for simulating complex chip designs on reconfigurable logic devices like FPGAs are limited by insufficient capacity and complex communication links, leading to high costs and inefficiencies in productivity and simulation flexibility.
Innovation Solution
A synchronization apparatus and method using a backplane and synchronizer to manage communication and timing across multiple partitions, allowing decentralized synchronization with a predetermined time window to align simulation participants, enabling efficient communication and flexible simulation of complex systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based simulations are used to check chip design functionality, then simulation flexibility and adaptability are improved, but simulation speed and productivity deteriorate
Solution Approach 1:
The patent divides the chip design into multiple partitions that can be simulated in parallel on different FPGAs. Each partition is independently simulated while maintaining synchronization through time window mechanisms, enabling both flexibility and speed by distributing the simulation workload across multiple hardware devices rather than using a single software simulator.
2Productivity
If multiple FPGAs are used to accommodate very complex chip designs, then simulation capacity and productivity are improved, but system complexity and cost worsen
Solution Approach 1:
The patent employs a universal time window synchronization mechanism that works across different FPGA partitions and simulation configurations. This standardized approach allows multiple FPGAs to be coordinated without requiring complex custom communication protocols or synchronization logic for each partition, thereby reducing overall system complexity while maintaining high simulation capacity.
3Reliability
If centralized synchronization is used across all partitions, then synchronization precision and reliability are improved, but communication overhead and time loss worsen
Solution Approach 1:
The patent pre-establishes time windows with predetermined durations before the simulation runs. Each partition knows in advance when it needs to synchronize with others, allowing them to prepare for synchronization events without requiring continuous centralized coordination. This preliminary configuration reduces real-time communication overhead while maintaining precise synchronization through the pre-calculated time window structure.
Data Source
AI summary
An apparatus for synchronizing participants of a simulation, including: a plurality of partitions, a backplane, and a synchronizer. Each partition is configured to run a respective simulation participant independently from other simulation participants. The backplane connects the plurality of partitions and is configured to transfer data between the plurality of partitions. The data include time stamps indicating a partition time of a simulation participant on at least one partition. The synchronizer is configured to synchronize the multiple partitions by stopping the running simulation participant of the at least one partition, when a time stamp of the running simulation participant is outside a synchronization window. The synchronization window has a predetermined time length indicating a range of acceptable time stamps (T1, T2) and starts with time (T0) associated with a time stamp of a slowest running simulation participant.