Differentiated Partitioned Source-Drain Contacts for FinFET Scaling
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in achieving increased device density and performance while navigating the limitations of lithographic processes, particularly in scaling down feature dimensions and fabricating terminals for vertically-oriented devices, where conventional methods face issues with interconnect dimensions, contact resistance, and edge-placement errors.
Innovation Solution
The implementation of self-aligned connections to the back-side of devices allows for relaxed edge-placement error requirements, enabling the fabrication of interconnects with looser pitch and larger width, which simplifies power delivery and reduces manufacturing costs, and involves the use of dual epitaxial connections and differentiated neighboring partitioned source or drain contact structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern building blocks, then manufacturing precision is maintained, but device density and scalability are limited due to overwhelming constraints on feature size and spacing
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically-oriented devices, enabling increased device density by utilizing the vertical dimension. The finFET structure with channel length substantially normal to the substrate surface allows more devices to be packed in a given footprint area while maintaining lithographic constraints.
Solution Approach 2:
The source and drain contact structures are partitioned into multiple segments (first conductive contact structure with first and second portions, second conductive contact structure with third and fourth portions) that can be independently formed and differentiated. This segmentation allows optimized electrical connections to different regions of the vertically-oriented devices.
2Productivity
If feature dimensions are scaled down to increase device density, then more devices fit on chip, but lithographic constraints become overwhelming and manufacturing precision deteriorates
Solution Approach 1:
By moving to vertically-oriented devices with channel lengths normal to the substrate, the patent reduces the lateral footprint requirements. This dimensional transition allows device density to increase without proportionally reducing lithographic feature sizes in the lateral plane, thereby maintaining manufacturing precision while improving productivity.
3Manufacturing precision
If self-aligned connections are implemented to the back-side of devices, then edge-placement error requirements are relaxed, but device complexity increases
Solution Approach 1:
The conductive contact structures are divided into multiple portions (first portion and second portion of first contact structure, third and fourth portions of second contact structure) with different compositions. This segmentation enables self-aligned formation processes where each portion can be independently optimized and formed with relaxed alignment tolerances, ultimately simplifying the overall manufacturing precision requirements.
Solution Approach 2:
Different compositions are used in different portions of the contact structures (e.g., first composition in first portion, second composition in second portion). This local differentiation allows each region to be optimized for its specific function while enabling self-aligned formation processes that relax edge-placement error requirements across the overall structure.
4Reliability
If differentiated neighboring partitioned contact structures are used, then signal and power delivery performance is improved, but manufacturing complexity increases
Solution Approach 1:
Different compositions are assigned to different portions of the contact structures based on their specific functional requirements. This local quality differentiation improves signal and power delivery performance by optimizing each contact region for its particular role while utilizing self-aligned formation processes to manage manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves signal and power delivery performance, lowers interconnect costs, and enables more aggressive scaling of device dimensions without compromising manufacturing complexity.
Implementation Method 1
the first and second compositions are removed to reveal a back-side of the device
Implementation Method 2
dual epitaxial connections
Data Source
Figure 1A~1C
Figure 1D~1F
Figure 1G~1H
AI summary
Integrated circuit structures having differentiated neighboring partitioned source or drain contact structures are described. An integrated circuit structure includes a first gate stack over a first fin, and a second gate stack over a second fin. First and second epitaxial source or drain structures (120) are at first and second ends of the first fin. Third and fourth epitaxial source or drain structures (112) are at first and second ends of the second fin. A first conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures, and has a first portion (122) partitioned from a second portion (128). A second conductive contact structure is coupled to one of the third or the fourth epitaxial source or drain structures, and has a first portion (114) partitioned from a second portion (126). The second conductive contact structure is neighboring the first conductive contact structure and has a composition different than a composition of the first conductive contact structure.