Partitioned Package Substrate Layout to Mitigate ASIC Warpage
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Solution Overview
Problem
The increasing complexity and cost of advanced semiconductor packaging, particularly for large-die ASICs, due to low production yield and warpage issues in package substrates, necessitate a cost-effective and reliable solution.
Innovation Solution
A semiconductor package using substrate block integration (SBI) with a partitioned package substrate composed of discrete substrates arranged side-by-side, connected through conductive elements like micro-bumps or copper pillars, and adjoined with a gap-filled adhesive, allowing for improved flexibility and reduced warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a large-die ASIC is packaged using traditional advanced packaging methods, then the package can accommodate the large die, but the production yield decreases and warpage issues occur
Solution Approach 1:
The package substrate is divided into multiple smaller substrate blocks (first substrate block, second substrate block, third substrate block, fourth substrate block) arranged in a 2x2 grid pattern. Each substrate block independently supports a portion of the large-die ASIC, preventing warpage and improving production yield while maintaining the ability to accommodate the large overall package area
2Area of stationary object
If a large-die ASIC is packaged using traditional advanced packaging methods, then the package can accommodate the large die, but warpage issues occur
Solution Approach 1:
The substrate is segmented into multiple smaller substrate blocks that are arranged in a grid pattern. This segmentation reduces the continuous substrate area, thereby minimizing thermal expansion differences and mechanical stress that cause warpage, while still providing sufficient support for the large-die ASIC
Solution Approach 2:
Different substrate blocks can have different properties optimized for their local requirements. The substrate blocks are connected through conductive elements that provide both mechanical support and electrical connectivity, allowing local optimization of each block while maintaining overall package stability
3Device complexity
If traditional packaging methods are used for large-die ASICs, then the package structure is simple, but the design flexibility decreases
Solution Approach 1:
The segmented substrate block structure enables modular design where each substrate block can be independently configured and optimized for specific functions. This modularity provides design flexibility for accommodating different die configurations, interconnect requirements, and thermal management needs while maintaining a relatively simple overall package structure
Solution Approach 2:
The substrate blocks serve multiple functions simultaneously: they provide mechanical support for the ASIC, establish electrical connections through conductive elements, enable thermal management pathways, and offer design flexibility for different package configurations. This multi-functionality increases adaptability without proportionally increasing structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances design flexibility, reduces production costs, and mitigates warpage issues, while maintaining electrical connectivity and reliability.
Implementation Method 1
the discrete substrates are adjoined together by using an adhesive that fills into the gap
Implementation Method 2
the at least one integrated circuit die is electrically connected to the partitioned package substrate through a plurality of conductive elements. Preferably, the conductive elements comprise micro-bumps, copper bumps or copper pillars
Implementation Method 3
A plurality of solder balls is mounted on a second surface of the partitioned package substrate opposite to the first surface
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
A semiconductor package (1) includes a partitioned package substrate that is composed of multiple discrete substrates (10a, 10c, 10e) arranged in a side-by-side manner. The discrete substrates (10a, 10c, 10e) include a central substrate (10e) and peripheral substrates (10a, 10c) surrounding the central substrate (10e). At least one integrated circuit die (20) is mounted on a first surface (S 1) of the partitioned package substrate. A plurality of solder balls (SB) is mounted on a second surface (S2) of the partitioned package substrate opposite to the first surface (S 1).