Partitioned Package Substrate Layout to Reduce Warpage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor packages with large dies face challenges such as high production costs, low yield, and warpage issues due to complex chip design and substrate size, particularly in advanced packaging technologies like 7 nm, 5 nm, and 3 nm geometries.
Innovation Solution
A semiconductor package using substrate block integration (SBI) with a partitioned package substrate composed of smaller, side-by-side arranged substrate parts, connected by conductive elements and adjoined with gaps, featuring integrated circuit dies and optional dummy or memory dies, encapsulated by a lid and mold cap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large-die semiconductor package is used to meet growing consumer demand for smart devices and data centers, then the package size increases to accommodate more functions, but production costs increase and manufacturing yield decreases
Solution Approach 1:
The package substrate is divided into multiple smaller substrate blocks that are arranged in a mosaic pattern. Each substrate block can be manufactured and tested independently, improving manufacturing yield. The substrate blocks are then assembled together to form the complete large-die package, maintaining the required functionality while avoiding the yield issues associated with manufacturing a single large substrate.
2Adaptability or versatility
If a large-die semiconductor package is used to accommodate more functions, then the package area increases, but warpage issues occur due to substrate stress
Solution Approach 1:
The large package substrate is segmented into multiple smaller substrate blocks. Each small block has reduced internal stress and is less prone to warpage. The blocks are arranged in a mosaic pattern with gaps between them, allowing independent stress management. This segmentation approach maintains the overall large package area needed for functionality while eliminating warpage issues through distributed stress management.
Solution Approach 2:
Gaps are introduced between adjacent substrate blocks as intermediary spaces. These gaps act as stress relief zones that prevent stress accumulation and warpage propagation across the entire package. The gaps may be filled with adhesive or molding compound to secure the blocks while maintaining stress management benefits.
3Area of stationary object
If a large-die semiconductor package is used to meet networking equipment and server requirements, then the package size exceeds 4500 mm², but production costs increase due to complex chip design
Solution Approach 1:
The manufacturing process is segmented into two stages: first, multiple small substrate blocks are manufactured using standard, cost-effective processes; second, these blocks are assembled into the final large-die package. This segmentation allows the use of proven, lower-cost manufacturing processes for each block rather than requiring expensive and complex processes for a single large substrate, thereby reducing overall production costs while achieving the required package area.
Solution Approach 2:
The substrate blocks are manufactured and pre-tested as independent units before final assembly. This preliminary action allows for early detection and correction of manufacturing issues at a lower cost, and enables parallel manufacturing of multiple blocks to improve production efficiency. The pre-assembled blocks are then integrated into the final package configuration, streamlining the overall manufacturing process.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
A semiconductor package (1) includes a partitioned package substrate (10) composed of substrate parts (10a, 10b) arranged in a side-by-side manner; an integrated circuit die (20) mounted on a first surface (S1) of the partitioned package substrate (10); and solder balls (SB) mounted on a second surface (S2) of the partitioned package substrate (10) opposite to the first surface (S1).