Partitioned Substrates with Interconnect Bridges for Cost Reduction

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Solution Overview

Problem

The increasing demand for higher speed Serializer/Deserializer (SerDes) lanes in wired network switching applications leads to larger substrate sizes, resulting in exponential cost increases due to the need for more ball grid arrays (BGAs) and isolation BGAs, making current substrate sizes a significant driver of cost.

Innovation Solution

The use of partitioned substrates with high-density interconnect bridges that physically and electrically connect multiple substrates and chips, allowing for smaller substrate sizes while maintaining high signal integrity and reducing costs by accommodating the same number of BGAs as larger substrates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If substrate size is increased to accommodate more BGAs and isolation BGAs for higher speed SerDes lanes, then the number of supported signals and isolation is improved, but substrate cost increases exponentially

Engineering Contradiction:
Improvenumber of BGAs and isolation BGAsVSAvoidsubstrate cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The invention divides a single large substrate into multiple smaller substrate modules (e.g., four 75mm substrates instead of one large substrate). Each module contains a subset of BGAs and can be independently manufactured and tested. The modules are then interconnected through interconnect bridges to form a complete functional unit, thereby reducing the cost of individual substrates while maintaining the total signal capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention implements a hierarchical structure where multiple smaller substrate modules are nested within a larger system architecture. Each module is self-contained with its own chips and interconnects, and multiple modules are combined through interconnect bridges to create the full functionality of a larger substrate system, enabling cost-effective scaling.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If substrate size is increased to accommodate more BGAs for high signal count applications, then signal capacity is improved, but substrate size becomes a main driver of increased cost above 75 mm

Engineering Contradiction:
Improvesignal countVSAvoidsubstrate size
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The invention segments the large substrate area into multiple smaller substrate modules, each staying below the 75mm cost threshold. By distributing the total signal count across multiple modules (e.g., 15 BGAs distributed across four modules), the system achieves high signal capacity without any single substrate exceeding the critical size threshold where costs escalate.

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If multiple smaller substrates are used instead of a single large substrate, then substrate cost is reduced, but device complexity increases due to interconnect bridges

Engineering Contradiction:
Improvesubstrate costVSAvoidinterconnect bridge structure
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The invention introduces interconnect bridges as intermediary components that physically and electrically connect multiple substrate modules. These bridges serve as mediators that enable communication between modules while allowing each module to remain independently manufacturable and testable, thereby managing the complexity through modular interfaces rather than requiring a single complex large substrate.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11282806B2Partitioned substrates with interconnect bridge
Publication Date: 2022.03.22 MARVELL ASIA PTE LTD
  • US11282806B2 patent drawing
  • US11282806B2 patent drawing
  • US11282806B2 patent drawing

AI summary

The present disclosure relates to semiconductor structures and, more particularly, to partitioned substrates with interconnect bridge structures and methods of manufacture. The structure includes: a plurality of substrates; at least one chip bonded and electrically connected to each of the plurality of substrates; and an interconnect bridge that physically connects the plurality of substrates and electrically connects each of the plurality of chips bonded to each of the plurality of substrates.