Partitioned Systolic Array for Small-Matrix Throughput
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Solution Overview
Problem
The performance of matrix product operations in systolic arrays is degraded when the multiplier matrix is smaller than the array size, leading to reduced usage of processor elements and unnecessary power consumption due to multiply-add operations with zero.
Innovation Solution
Partition the systolic array into smaller sub-arrays and utilize a controller to manage the output signals of processing elements, allowing parallel matrix calculations across these partitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the systolic array processes matrix product operations with small multiplier matrices, then the array can handle various matrix sizes, but the performance is degraded due to reduced processor element usage and unnecessary power consumption
Solution Approach 1:
The patent divides the systolic array into multiple partitions (first systolic array and second systolic array) positioned downstream of each other. This segmentation allows the array to process multiple matrix operations simultaneously by routing different data streams to different partitions, thereby maintaining high processor element usage even when handling small multiplier matrices, and eliminating unnecessary power consumption from unused elements.
2Productivity
If the systolic array uses all processor elements for matrix operations, then the calculation performance is maximized, but power is wasted when processing small matrices that require fewer elements
Solution Approach 1:
The patent introduces a controller that dynamically switches output signals from processors based on the operation requirements. The controller routes signals to appropriate partitions downstream, enabling the system to activate only the necessary processor elements for each specific matrix operation size, thereby avoiding power waste while maintaining calculation performance.
3Productivity
If the systolic array is partitioned into multiple sub-arrays, then the number of usable processor elements increases for small matrices, but the device complexity increases
Solution Approach 1:
The patent combines multiple systolic array partitions into a single integrated structure where the first and second systolic arrays are positioned downstream of each other within the same array framework. This merging approach allows the system to treat multiple partitions as a unified resource, managing them through a single controller that routes signals appropriately, thereby increasing usable processor elements without proportionally increasing overall device complexity.
Data Source
AI summary
A systolic array includes a plurality of processing elements, the systolic array including a first systolic array and a second systolic array that are obtained by partitioning the systolic array, and a controller. The second systolic array is positioned downstream of the first systolic array. Each of the plurality of processing elements includes a selector that selectively outputs an output signal, and the controller switches the output signals of the plurality of processing elements from the selectors between first processing elements positioned on a last stage of the first systolic array and second processing elements, the second processing elements being processing elements of the second systolic array and processing elements of the first systolic array except for the first processing elements.