Partitioned Via Structure for PCB Trace Density
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Solution Overview
Problem
Conventional metal vias on circuit boards occupy significant surface area, leading to increased spacing between electrical traces and potential impedance discontinuities, especially in high-data-rate applications, due to the need for larger lead lands and diversion of parallel traces through separate vias.
Innovation Solution
The implementation of partitioned vias, which allow multiple traces to be coupled through a single via hole by partitioning the sidewalls and using a dielectric plug for electrical isolation, reducing the surface area footprint and maintaining consistent trace spacing without impedance issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional metal vias are used on circuit boards, then electrical connections between layers are established, but significant surface area is occupied leading to increased spacing between traces and potential impedance discontinuities
Solution Approach 1:
The via structure is segmented into multiple functional zones: a first via portion extending through the first dielectric layer, a second via portion extending through the second dielectric layer, and a connection portion joining them. This segmentation allows each portion to be optimized independently, reducing the overall surface area footprint while maintaining electrical continuity and impedance control across layered circuit board structures.
2Reliability
If larger lead lands are used to accommodate conventional vias, then via connections are secured, but spacing between electrical traces is reduced leading to impedance discontinuities
Solution Approach 1:
The via connection structure utilizes vertical dimensionality by extending through multiple dielectric layers with connection portions at intermediate levels. This three-dimensional configuration secures reliable via connections through improved mechanical anchoring and electrical contact across layers, while the optimized footprint minimizes horizontal space occupation, thereby maintaining adequate spacing between adjacent electrical traces and preventing impedance discontinuities.
3Reliability
If parallel traces are diverted through separate vias to avoid shorting, then electrical isolation is maintained, but surface area consumption increases
Solution Approach 1:
Multiple via functions are merged into a single integrated via structure that handles multiple electrical connections and isolation requirements simultaneously. The via includes connection portions at different levels that can serve multiple traces, eliminating the need for separate vias for each connection while maintaining electrical isolation between parallel traces through the dielectric layers. This consolidation reduces the total surface area consumed by via structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables closer trace alignment and differential signal transmission without impedance discontinuities, conserving surface area on circuit boards and improving data transfer efficiency in high-data-rate applications.
Implementation Method 1
a dielectric plug formed in the via hole and electrically isolated from the metal wall plating
Data Source
AI summary
Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a non-conductive layer and a partitioned via formed in a portion of the non-conductive layer. The non-conductive layer includes a top side, a bottom side, and a via hole extending between the top and bottom sides and including a sidewall having a first section a second section. The partitioned via includes a first metal interconnect within the via on the first section of the sidewall and a second metal interconnect within the via hole on the second section of the sidewall and electrically isolated from the first metal interconnect. In another embodiment, the first metal interconnect is separated from the second metal interconnect by a gap within the via hole.