Parylene Sidewall Passivation for Short-Circuit-Resistant Chips
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Solution Overview
Problem
Conventional surface-mounted electronic chips face challenges in ensuring electrical reliability and preventing short-circuits, particularly at the connection interface with outer devices, due to the lack of adequate insulation on the side flanks of the chip.
Innovation Solution
The implementation of a parylene-based passivation layer covering both the front face and side flanks of the semiconductor substrate, with specific methods for deposition and trench formation to ensure comprehensive insulation and mechanical protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a passivation layer is formed only on the front face of the chip, then the manufacturing process is simple, but electrical insulation on the side flanks is insufficient leading to short-circuit risks
Solution Approach 1:
The passivation coverage is extended from the traditional two-dimensional front face to include the three-dimensional side flanks of the chip. The second passivation layer is deposited to cover the lateral surfaces, creating a multi-dimensional insulation barrier that prevents short-circuits between adjacent chips while maintaining manufacturing feasibility through vapor-phase deposition processes.
Solution Approach 2:
The solution employs a nested structure with two passivation layers: the first passivation layer covers the front face with connection metallization openings, while the second passivation layer covers the side flanks and extends to contact the first layer. This nested arrangement creates comprehensive electrical insulation without requiring complete redesign of the manufacturing process.
2Reliability
If comprehensive passivation covering side flanks is implemented, then short-circuit prevention is improved, but the manufacturing process complexity increases
Solution Approach 1:
The mechanical approach of forming passivation layers through multiple sequential deposition steps is replaced by vapor-phase deposition processes. The vapor-phase methods allow the second passivation layer to automatically conform to and cover the side flanks of the chip, eliminating the need for complex mechanical masking and alignment operations while ensuring complete insulation coverage.
3Reliability
If parylene material is used for the second passivation layer, then electrical insulation performance is enhanced, but deposition process complexity increases
Solution Approach 1:
The deposition process utilizes phase transitions of parylene material from vapor phase to solid phase. By heating parylene to its sublimation point and allowing the vapor to condense on the chip surfaces, the process achieves uniform coating on complex geometries including side flanks, eliminating the need for multiple deposition steps or complex equipment while maintaining high insulation performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances electrical reliability and reduces the risk of short-circuits by limiting mechanical contact between brazing material and the substrate, thereby improving the overall performance and integration of electronic chips in various applications.
Implementation Method 1
a vaporization step during which solid dimers of parylene are heated and vaporized into a dimer gas
Implementation Method 2
a pyrolysis step during which the dimer gas is processed by pyrolysis to transform the dimers in their monomer forms
Implementation Method 3
a depositing step during which the monomer gas deposits on all exposed surfaces
Data Source
AI summary
An electronic chip including a semiconductor substrate in and on which an integrated circuit is formed at least one connection metallization of the integrated circuit formed on the side of a front face of the semiconductor substrate and a first passivation layer covering the front face of the semiconductor substrate, the first passivation layer including openings in line with the connection metallization of the integrated circuit The chip having a second passivation layer covering the side flanks of the semiconductor substrate, the second passivation layer being made of a parylene, and the first passivation layer and the second passivation layer being in contact with each other on the side of the front face of the semiconductor substrate. Methods of making a device are also provided.