Multi-PASID Scalable IOV Routing for Bandwidth Efficiency
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Solution Overview
Problem
Scalable Input/Output Virtualization (IOV) systems with a single PASID per Assignable Device Interface (ADI) face performance overheads due to inability to distinguish between host and guest VM address spaces, leading to inefficiencies in data access and bandwidth usage, especially in smart controller and accelerator IO usages.
Innovation Solution
Implementing multi-PASID scalable IOV devices with a separate PASID for descriptor fetches (C-PASID) and data fetches (D-PASID), and utilizing a hub to steer traffic based on PASIDs to either host memory or intermediate device memory, optimizing performance by eliminating unnecessary data copies and enhancing bandwidth efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single PASID is used per ADI for all memory requests, then the system structure is simple, but performance overhead increases and the system cannot distinguish between host and guest VM address spaces
Solution Approach 1:
The patent segments the single PASID into multiple PASIDs (host PASID and guest PASID) that can be selectively used. The hub device receives memory requests and determines whether to use the host PASID or guest PASID based on the request type (descriptor fetch vs. data fetch), thereby segmenting the address space identification function to resolve the contradiction between structural simplicity and performance.
2Device complexity
If a single PASID is used per ADI, then device configuration is simplified, but bandwidth efficiency deteriorates due to inability to distinguish address spaces
Solution Approach 1:
The hub device acts as an intermediary between the ADI and the memory system. It receives memory requests from the ADI, determines the appropriate PASID to use based on the request type, and forwards the request with the correct PASID tag. This intermediary function enables efficient bandwidth utilization by preventing address space confusion without requiring complex configuration at the ADI level.
3Ease of operation
If smart controller local memory is used for descriptor storage, then descriptor fetch is enabled, but bandwidth and capacity taxes increase on local memory
Solution Approach 1:
The patent applies local quality by using different PASIDs for different types of memory accesses. Descriptor fetches use the host PASID to access host memory, while data fetches use the guest PASID to access guest memory directly. This differentiation optimizes the use of smart controller local memory by reducing unnecessary traffic and capacity consumption for descriptor operations.
Data Source
AI summary
Methods and apparatus for PASID-based routing extension for Scalable IOV systems. The system may include a Central Processing Unit (CPU) operatively coupled to a scalable Input/Output Virtualization (IOV) device via an in-line device such as a smart controller or accelerator. A Control Process Address Space Identifier (C-PASID) associated with a first memory space is implemented in an Assignable Device Interface (ADI) for the IOV device. The ADI also implements a Data PASID (D-PASID) associated with a second memory space in which data are stored. The C-PASID is used to fetch a descriptor in the first memory space and the D-PASID is employed to fetch data in the second memory space. A hub embedded on the in-line device or implemented as a discrete device is used to steer memory access requests and/or fetches to the CPU or to the in-line device using the C-PASID and D-PASID. IOV devices include multi-PASID helper devices and off-the-shelf devices such as NICs with modified ADIs to support C-PASID and D-PASID usage.