PASID State Entries for TLB Shoot-down in Heterogeneous Systems
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Solution Overview
Problem
In multi-core systems with heterogeneous devices, efficient translation look-aside buffer (TLB) shoot-downs are hindered by communication congestion and limited capabilities of heterogeneous processing devices, leading to performance overhead and restricted application support due to inadequate handling of page faults and TLB invalidations.
Innovation Solution
Implementing a memory management unit coupled with a TLB to store virtual address translation entries and maintain PASID state entries with active reference and lazy-invalidation states, allowing for atomic modifications and synchronized TLB updates, thereby optimizing TLB shoot-downs across heterogeneous devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a broadcast invalidation message is sent to all devices in the system, then TLB shoot-down is achieved, but communication congestion occurs
Solution Approach 1:
The patent segments the invalidation process by introducing PASID-specific state entries that track which heterogeneous devices have active translations for each process address space. Instead of broadcasting to all devices, invalidation messages are selectively sent only to devices with active PASID states, dividing the monolithic broadcast into targeted individual communications.
Solution Approach 2:
The patent introduces an intermediary mechanism - the PASID state entry in the memory management unit - that mediates between the TLB and heterogeneous devices. This intermediary tracks device activity states and controls message routing, preventing direct broadcast congestion while ensuring complete invalidation through selective messaging.
2Reliability
If pages are locked down in memory to support heterogeneous processing devices, then TLB shoot-down capability is improved, but physical memory requirements increase
Solution Approach 1:
The patent performs preliminary action by pre-establishing PASID state entries in the memory management unit that track which heterogeneous devices have active translations. This preliminary tracking structure enables selective invalidation without requiring pages to be locked in memory, allowing the system to prepare invalidation paths in advance rather than locking pages permanently.
3Adaptability or versatility
If software on homogeneous processor cores sets up page tables for heterogeneous devices, then virtual memory sharing is enabled, but performance overhead increases
Solution Approach 1:
The patent enables self-service by allowing heterogeneous devices to autonomously manage their own translation validity states through PASID tracking. The memory management unit automatically tracks which devices have active translations and handles invalidation selection, eliminating the need for software on homogeneous processor cores to manually manage page tables for each device, thus reducing performance overhead while maintaining adaptability.
4Productivity
If lazy invalidation scheme is used for homogeneous processor cores, then unnecessary TLB shoot-down activity is reduced, but heterogeneous processing devices cannot track active processes
Solution Approach 1:
The patent applies universality by extending the lazy invalidation concept to heterogeneous processing devices through the PASID state entry mechanism. The PASID state serves multiple functions: it tracks process activity for lazy invalidation decisions, identifies which devices need invalidation messages, and enables selective shoot-down. This multi-functional approach allows heterogeneous devices to participate in lazy invalidation without losing process activity tracking capability.
Data Source
AI summary
Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.