PASID Table Hardware for Efficient Address Space Access
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Solution Overview
Problem
Existing computing systems face inefficiencies when accessing multiple address spaces due to context switches and permission checks, particularly with instructions like the enqueue command instruction that use process address space identifiers (PASIDs), leading to difficulties in accessing shared virtual memory and interacting with devices that have different PASIDs.
Innovation Solution
The implementation of processor-internal hardware structures and user-level instructions that utilize a PASID handle to enable efficient access to multiple address spaces without switching the PASID stored in a model-specific register (MSR), allowing non-privileged software clients to issue work requests to shared work queues across devices with different PASIDs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If context switches are used to access different address spaces with different PASIDs, then permission checks can be performed, but system efficiency deteriorates due to the overhead of context switching
Solution Approach 1:
The patent applies preliminary action by pre-establishing a PASID table structure in hardware that maps PASID handles to actual PASID values before they are needed during instruction execution. This allows the system to prepare address space translation information in advance, eliminating the need for costly context switches when accessing different address spaces during normal operation.
Solution Approach 2:
The patent introduces an intermediary mechanism - a PASID table stored in hardware - that acts as a mediator between the PASID handle (used in instructions) and the actual PASID value (used for permission checking). This intermediary structure allows efficient translation between the two without requiring context switches, resolving the contradiction between maintaining permission checking reliability and improving system efficiency.
2Adaptability or versatility
If PASID is switched in MSR to access different address spaces, then different devices can be accessed, but instruction execution time increases due to MSR switching overhead
Solution Approach 1:
The patent extracts the PASID switching function from the MSR (model-specific register) and relocates it to a dedicated PASID table in hardware. This extraction allows the instruction to use a stable PASID handle while the actual PASID value is retrieved from the table, eliminating the time-consuming MSR switch operation and reducing instruction execution time while maintaining adaptability to different address spaces.
Solution Approach 2:
The patent uses a copying mechanism where the PASID table stores copies of PASID values indexed by PASID handles. Instead of switching the actual PASID in MSR, the system copies the relevant PASID value from the table into the execution path, allowing rapid access to different address spaces without the time overhead of MSR switching operations.
3Productivity
If hardware structures are added to support multiple address spaces, then access efficiency improves, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the PASID management function into discrete components: a PASID table structure with indexed entries, a table pointer register, and integration points with the instruction execution unit. This segmented architecture achieves efficient multi-address-space access while keeping each individual component relatively simple and modular, minimizing the overall increase in device complexity.
Data Source
AI summary
In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.