Pass-Gate Clock Gating Circuit for Lower Clock Power
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Solution Overview
Problem
In digital systems, a significant portion of power dissipation occurs due to charging and discharging load capacitance in clock distribution grids, and existing clock gating techniques either increase clock load in un-gated portions or suffer from poor timing and power efficiency.
Innovation Solution
The implementation of pass-gate based integrated clock gate circuits that perform AND and OR functions, which are fully interruptible, enabling robust low voltage operation and tolerance to process variations, reducing clock power and pin capacitance while improving setup times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional clock gating techniques are used, then clock power is reduced, but clock load in un-gated portions increases
Solution Approach 1:
The patent introduces an intermediate clock gating buffer between the clock source and the gated/un-gated logic portions. This buffer acts as a mediator that can selectively drive different clock loads based on the gating state, preventing the full clock load from being placed on un-gated portions when gating is active, thus reducing both clock power and excessive clock load simultaneously
2Loss of energy
If clock gating is implemented, then dynamic power dissipation is reduced, but setup time performance deteriorates
Solution Approach 1:
The clock gating buffer is designed to anticipate and prepare for clock transitions by pre-charging or pre-discharging internal nodes before the actual clock edge arrives. This preliminary action ensures that the buffer is ready to switch quickly when the clock edge occurs, maintaining fast setup times while still achieving power reduction through clock gating
3Loss of energy
If traditional AND logic clock gates are used, then clock power is reduced, but device area increases
Solution Approach 1:
The patent merges the clock gating buffer functionality with the clock distribution network infrastructure, utilizing existing buffer structures and routing resources. By integrating the gating function into the existing clock distribution architecture rather than adding separate discrete gating circuits, the solution achieves effective clock power reduction without proportionally increasing device area
Data Source
AI summary
An apparatus is provided which comprises: a first inverter to receive a clock; a pass-gate coupled to the first inverter; a second inverter coupled to the pass-gate and to provide an output clock; and a device coupled to the second inverter and the pass-gate, wherein the transistor and the pass-gate are controllable by a logic that depends on logic values of at least two signals (e.g., an enable and the clock).