Pass Gate Driver With Dual-Path Charging for Fast Stable Turn-On

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Solution Overview

Problem

Digital low dropout (LDO) regulators experience 'dead time' due to slow turn-on of pass gate switches, which affects stability due to parasitic inductance and results in strong transients and ringing in the regulated output voltage.

Innovation Solution

A driver circuit with a low-resistance charging path, a high-resistance charging path, and an inverter configuration that enables fast turn-on and slow slew rate, reducing transients by quickly charging the pass gate transistor to its threshold voltage and then maintaining a slow ramp to prevent strong transients.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a shallow ramp in gate voltage is used to turn on pass gate switches, then strong transients and ringing in the regulated output voltage are prevented, but the turn-on time increases and introduces dead time affecting stability

Engineering Contradiction:
Improvetransients and ringing in regulated output voltageVSAvoiddead time during gate voltage charging
Core Design Contradiction:
Object-affected harmful factorsVSLoss of time

Solution Approach 1:

The charging path for the gate voltage is segmented into two distinct paths: a low-resistance charging path for rapid voltage rise and a high-resistance charging path for slow slew rate control. This segmentation allows the system to achieve both fast turn-on and transient suppression by selectively activating different paths based on the required operation phase

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The driver circuit dynamically switches between different charging paths based on the gate voltage level. An inverter monitors the gate voltage and automatically transitions from the low-resistance path to the high-resistance path when the threshold voltage is reached, optimizing both speed and stability without manual intervention

Inventive Principle:
Principle #15Dynamics

2Object-generated harmful factors

If a slow turn-on with shallow ramp is used, then current transients through pass gate switches are reduced, but the dead time increases affecting LDO regulator stability

Engineering Contradiction:
Improvecurrent transients through pass gate switchesVSAvoidstability of digital LDO regulator
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The low-resistance charging path is activated in advance to quickly charge the gate voltage to the threshold level, preparing the pass gate switch for conduction. This preliminary fast charging action reduces the overall dead time while the subsequent high-resistance path maintains stable operation, preventing the stability issues associated with prolonged slow turn-on

Inventive Principle:
Principle #10Preliminary action

3Loss of time

If fast turn-on is implemented to reduce dead time, then stability of digital LDO regulator improves, but strong transients and ringing occur in the regulated output voltage

Engineering Contradiction:
Improvedead time during gate voltage chargingVSAvoidringing in regulated output voltage
Core Design Contradiction:
Loss of timeVSObject-affected harmful factors

Solution Approach 1:

The high-resistance charging path acts as an intermediary mechanism that takes over from the low-resistance path once the threshold voltage is reached. This intermediary path provides a controlled slew rate that prevents direct coupling of fast switching edges to the output, thereby eliminating ringing while maintaining the stability benefits of fast initial turn-on

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11901803B2Pass gate driver
Publication Date: 2024.02.13 TEXAS INSTRUMENTS INC
  • US11901803B2 patent drawing
  • US11901803B2 patent drawing
  • US11901803B2 patent drawing

AI summary

A driver includes a low-resistance charging path between a supply voltage rail and a first output node, a high-resistance charging path between the supply voltage rail and the first output node, an inverter coupled to the first output node and configured to enable and disable the low-resistance charging path, and a high-resistance discharging path between the first output node and a second output node. The first output node is coupled to a control terminal of a pass gate transistor in some implementations. The low-resistance charging path charges a voltage on the first output node to a threshold voltage of the pass gate transistor, and the high-resistance charging path charges the voltage on the first output node greater than the threshold voltage of the pass gate transistor. The high-resistance discharging path discharges the voltage on the first output node.