Pass-Gate Multiplexer Scan Coverage Without High-Impedance States
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Solution Overview
Problem
Pass-gate multiplexers in high-speed processors face challenges in detecting faults, leading to undetected high-impedance output states, which result in computational errors and hinder the distinction between good and faulty chips, particularly in achieving ultra-low defective parts per million rates.
Innovation Solution
A novel tristate or pass-gate based multiplexer circuit structure with full scan coverage capability is introduced, utilizing pull-up and pull-down transistors or combinational logic to create deterministic output states, avoiding high-impedance logic states and enhancing fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pass-gate multiplexers are used in high-speed processors, then circuit speed and performance are improved, but fault detection capability deteriorates due to undetected high-impedance output states
Solution Approach 1:
The patent introduces an intermediary circuit that monitors the select pins and control logic of pass-gate multiplexers. This intermediary detection mechanism identifies high-impedance states that would otherwise be undetected, allowing faulty chips to be distinguished from good chips while maintaining the high-speed performance of the pass-gate multiplexers.
2Device complexity
If conventional pass-gate multiplexer structures are used, then device complexity is reduced, but test coverage deteriorates due to inability to detect high-impedance states
Solution Approach 1:
The patent segments the multiplexer circuit into distinct functional blocks with defined interfaces. By dividing the circuit into selectable input paths and output sections, each controlled by specific select pins, the patent enables targeted fault detection at segment boundaries while maintaining overall structural simplicity.
Solution Approach 2:
The patent employs signal state changes (analogous to color changes) to indicate fault conditions. High-impedance states are detected through changes in voltage levels or signal characteristics at specific nodes, allowing test equipment to identify faulty chips through measurable signal variations without complex circuit modifications.
3Ease of operation
If high-impedance output states are allowed in pass-gate multiplexers, then circuit operation is simplified, but defect detection capability deteriorates
Solution Approach 1:
The patent implements feedback mechanisms that monitor the output states of pass-gate multiplexers and provide information about high-impedance conditions. This feedback allows the test system to detect when a select pin fault causes an unintended high-impedance state, enabling defect detection while maintaining simple circuit operation during normal functionality.
Data Source
AI summary
A tristate and pass-gate based multiplexer circuit structure is described with full scan coverage capability. The circuit provides deterministic state at its output avoiding high impedance (Z) logic states in silicon. This is realized using a pull-up transistors, pull-down transistors, or through stages of combinational logic combining the multiplexer selects/enables feeding a pull-up or pull-down transistors.