Pass-Through 3D Interconnects for Selective ESD Disablement
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Solution Overview
Problem
Conventional stacked microelectronic die packages face challenges in reducing volume while increasing capacity and performance, and they suffer from signal delays due to redundant electrostatic discharge (ESD) devices that are not selectively disableable without requiring different integrated circuit configurations.
Innovation Solution
The implementation of pass-through 3D interconnects and microelectronic dies with selectively disabled ESD devices, where ESD devices are disconnected during fabrication by forming dielectric liners and removing conductive paths, allowing for non-redundant ESD protection without additional manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple ESD devices are included in stacked microelectronic die packages for comprehensive protection, then reliability is improved, but device complexity and signal delays increase due to redundant components
Solution Approach 1:
The patent applies local quality by making ESD device inclusion selective rather than uniform across all dies. Each die is evaluated individually to determine whether it requires ESD protection based on its specific location and function in the stacked package, allowing comprehensive protection where needed while eliminating redundant devices elsewhere.
Solution Approach 2:
The patent implements dynamics by enabling flexible, post-fabrication selection of ESD devices. The selective disablement mechanism allows the ESD protection configuration to be dynamically adjusted based on actual package requirements, transitioning from a static, all-or-nothing approach to a flexible, needs-based configuration.
2Device complexity
If different integrated circuit configurations are used to selectively disable ESD devices, then device complexity is reduced, but manufacturing precision and productivity deteriorate due to additional configuration requirements
Solution Approach 1:
The patent applies segmentation by dividing the ESD device control into individual, independently controllable units. Each ESD device can be selectively disabled through physical separation or electrical isolation mechanisms, allowing precise control without requiring complex global reconfiguration of the integrated circuit.
Solution Approach 2:
The patent implements preliminary action by incorporating ESD disablement capability directly into the die fabrication process. The structural features enabling selective ESD device disablement are built into the die during manufacturing, allowing later selection without requiring additional fabrication steps or complex post-fabrication configuration procedures.
3Reliability
If redundant ESD devices are maintained in stacked die packages, then reliability is preserved, but volume increases and capacity is reduced
Solution Approach 1:
The patent applies local quality by providing ESD protection only in specific locations where it is actually needed within the stacked package. By evaluating each die's specific requirements and enabling selective ESD device inclusion, the patent eliminates redundant protection devices that would otherwise occupy unnecessary volume in the package structure.
Data Source
AI summary
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.