Pass-Through Clock Traces in Stacked Die Packages for Signal Integrity
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Solution Overview
Problem
Conventional semiconductor devices face signal integrity limitations and increased noise due to loading on clock signals as bandwidth increases, particularly in dual die package (DDP) semiconductor packages with physically longer clock traces that lead to errors like skew errors.
Innovation Solution
The implementation of pass-through clock traces in semiconductor devices, which reduce the load on clock signals by eliminating branches or stubs, allowing the clock signal to propagate directly between the package substrate and the semiconductor dies, thereby maintaining signal integrity even at higher data transfer rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional clock trace routing with branches or stubs is used in DDP packages, then clock signals can be distributed to multiple dies, but signal integrity deteriorates and loading increases as bandwidth increases
Solution Approach 1:
The patent extracts and removes the harmful branches or stubs from the clock trace routing. By eliminating these unnecessary trace extensions that cause signal reflections and loading, the clock signal path is simplified to a direct route through the package substrate, thereby maintaining signal integrity while still distributing clocks to multiple dies.
Solution Approach 2:
Instead of routing clock signals through traditional branched paths that terminate at each die, the patent inverts the approach by using a pass-through configuration where the clock trace continues directly through the package substrate without terminating. This reversal of the conventional routing topology eliminates signal reflections and reduces loading effects.
2Adaptability or versatility
If physically longer clock traces are used in DDP packages, then more dies can be connected, but noise increases and skew errors occur
Solution Approach 1:
The patent segments the clock distribution function into two parts: a short, direct pass-through trace in the package substrate that maintains signal integrity, and separate connection paths from each die to the substrate contacts. This segmentation allows multiple dies to be connected without requiring long individual trace lengths, thereby reducing noise and skew errors.
Solution Approach 2:
The package substrate acts as an intermediary with dedicated substrate contacts that receive clock signals directly from the PCB and distribute them to multiple dies. This intermediary structure eliminates the need for long clock traces within the package, reducing exposure to noise and skew errors while maintaining adaptability to connect multiple dies.
3Ease of operation
If traditional clock routing with branches is used, then clock signals reach multiple dies, but load on clock signals increases reducing bandwidth performance
Solution Approach 1:
The patent extracts and removes the branching structure from the clock trace that causes increased loading. By using a direct pass-through configuration, the clock signal does not need to drive multiple branched paths, significantly reducing the capacitive and inductive loading effects while still enabling clock delivery to multiple dies through separate substrate contacts.
Data Source
AI summary
Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.