Pass Transistor Control for Hot Hole Trapping in Memory Erase
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Solution Overview
Problem
Semiconductor memory devices face reliability issues during erase operations due to the introduction and trapping of hot holes in the channel layer, which can affect data integrity and accuracy, especially in unselected memory blocks.
Innovation Solution
The semiconductor memory device employs pass transistors coupled between global and local lines, with an address decoder configured to selectively turn on pass transistors, ensuring that unselected memory blocks maintain a high potential level of local word lines during erase operations, preventing hot holes from being introduced or trapped.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase operations are performed on semiconductor memory devices, then data storage capacity is maintained, but hot holes are introduced and trapped in the channel layer causing reliability issues
Solution Approach 1:
The patent applies preliminary anti-action by turning on pass transistors before and during erase operations to prevent hot holes from being introduced into the channel layer. By proactively establishing a conductive path through the pass transistors, the system counteracts the harmful effect of hot hole generation before it can occur, thereby maintaining data integrity while performing erase operations.
Solution Approach 2:
The pass transistors serve as intermediary elements between the global lines and local lines. These intermediaries provide a controlled pathway that allows erase operations to proceed while preventing hot holes from reaching and trapping in the channel layer of unselected memory blocks, thus resolving the reliability issue.
2Reliability
If pass transistors are turned on during erase operations, then hot hole introduction is prevented, but additional control circuitry is required
Solution Approach 1:
The pass transistors are integrated into the existing memory device architecture and serve multiple functions: they act as switches for selecting memory blocks, provide hot hole prevention pathways during erase operations, and maintain normal memory operation during read and write operations. This multi-functionality reduces the need for separate dedicated control circuitry.
Solution Approach 2:
The patent merges the hot hole prevention function with the existing pass transistor structure used for memory block selection. By combining these functions into a single control mechanism managed by the address decoder, the system avoids adding separate complex control circuits while achieving reliable erase operations.
3Reliability
If unselected memory blocks maintain high potential level during erase operations, then hot hole trapping is prevented, but energy consumption increases
Solution Approach 1:
The patent applies local quality by maintaining high potential level only in the specific regions where hot hole trapping would occur (unselected memory blocks connected to global lines), rather than throughout the entire memory device. The pass transistors enable selective potential maintenance only where needed, reducing unnecessary energy consumption in other regions.
Solution Approach 2:
Instead of maintaining high potential level across all memory blocks during erase operations, the system applies this action partially only to unselected blocks that are connected to active global lines. This partial action approach prevents hot hole trapping where necessary while avoiding excessive energy consumption in already-selected or inactive blocks.
Data Source
AI summary
The present disclosure relates to an electronic device, and more particularly, to a peripheral circuit, semiconductor memory device, and an operating method of the semiconductor memory device and/or peripheral circuit. The method of operating the semiconductor memory device may include turning on pass transistors.