Pass Transistor Wiring Inhibition Interval for Memory Reliability
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Solution Overview
Problem
Semiconductor memory devices face issues with slow failures and degraded cell voltage distribution characteristics due to increased coupling capacitances and parasitic resistances caused by reduced wiring line dimensions, leading to inefficient program voltage transfer and poor cell performance.
Innovation Solution
Incorporating a wiring inhibition interval in the wiring line layer that overlaps with the source and drain of pass transistors, while excluding certain wiring lines, to maintain the program voltage level and prevent reductions, thereby suppressing slow failures and improving cell voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If wiring line dimensions are reduced to increase integration density, then device integration is improved, but coupling capacitances and parasitic resistances increase causing slow failures and degraded cell voltage distribution
Solution Approach 1:
The patent extracts and removes wiring lines from the inhibition interval region that overlaps with the pass transistor source and drain. By taking out problematic wiring lines from this specific area, the coupling capacitance between wiring lines and pass transistor terminals is reduced, preventing voltage level degradation and slow failures while maintaining high integration density through reduced wiring line dimensions.
2Productivity
If wiring lines are disposed over pass transistor source and drain to increase wiring density, then wiring integration is improved, but program voltage transfer efficiency deteriorates due to increased coupling capacitance
Solution Approach 1:
The patent applies local quality by creating a spatial differentiation in wiring line disposition. The inhibition interval is established as a specific local region where wiring lines are excluded from overlapping with pass transistor source and drain terminals. This localized restriction reduces coupling capacitance in the critical voltage transfer path while allowing wiring lines to be densely packed in other regions, thus maintaining overall wiring density without compromising voltage transfer efficiency.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cell arrays accessed through a plurality of row lines and a plurality of bit lines; a pass transistor coupled to one of the plurality of row lines and configured to transfer an operating voltage to the one of the plurality of row lines; and a plurality of wiring lines disposed in a wiring line layer over the pass transistor. The wiring line layer includes a wiring inhibition interval which overlaps a source and a drain of the pass transistor. One or more of the plurality of wiring lines is disposed outside of the wiring inhibition interval.