Dynamic Pass Voltage Adjustment for 3D NAND Reliability
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Solution Overview
Problem
Memory devices experience reliability issues due to read window budget degradation, leading to increased bit errors as partially functional blocks in 3D NAND devices face challenges in maintaining accurate read results during program verify operations, especially after numerous program erase cycles.
Innovation Solution
A memory sub-system adaptively adjusts the default pass voltage applied to unselected wordlines during program verify operations, determining the functional status of blocks and applying specific voltage adjustments based on the number of program erase cycles to prevent read window budget degradation and reduce bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a default pass voltage is used during program verify operations, then the operation is simple and fast, but read window budget degradation occurs leading to increased bit errors
Solution Approach 1:
The patent implements dynamic pass voltage adjustment during program verify operations based on the number of program erase cycles. The pass voltage is changed from a fixed default value to a dynamic value that adapts to the wear state of the memory device, resolving the contradiction between maintaining simple operations and preventing read window budget degradation
Solution Approach 2:
The patent changes the pass voltage parameter based on program erase cycle count to maintain read accuracy. By adjusting this critical voltage parameter dynamically, the system prevents read window budget degradation without requiring complex hardware modifications, thus resolving the contradiction between reliability and device complexity
2Reliability
If the pass voltage is adjusted based on program erase cycles, then bit errors are reduced, but the operation time increases
Solution Approach 1:
The patent performs preliminary determination of the program erase cycle count before the program verify operation. This allows the system to pre-select the appropriate pass voltage adjustment value from a lookup table, avoiding time-consuming calculations during the verify operation itself and thus reducing the time penalty while maintaining improved reliability
Solution Approach 2:
The patent uses feedback from the program erase cycle count to automatically adjust the pass voltage. This feedback mechanism enables the system to adapt to wear without manual intervention or complex real-time monitoring, reducing bit errors while keeping the time overhead minimal through efficient feedback-based voltage selection
Data Source
AI summary
A request to perform a program operation on a set of vertically stacked memory cells of a memory device is received. A pass voltage adjustment value based on a number of program erase cycles (PECs) associated with the memory device is determined responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable. A default pass voltage is adjusted by the pass voltage adjustment value to generate an adjusted pass voltage. The program operation on the set of vertically stacked memory cells is performed using the adjusted pass voltage.