Pass Voltage Control for Program Disturb in Charge-Trapping Memory
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Solution Overview
Problem
In memory devices, particularly those with scaled-down features where the distance between word lines is less than 25 nm, program disturb occurs due to parasitic cells formed between memory cells, leading to an upshift in threshold voltage during read operations, especially affecting erased and lowest programmed state cells.
Innovation Solution
Optimizing pass voltages during programming by setting a higher pass voltage on later-programmed word lines and gradually lowering it, ensuring the difference between pass voltages is sufficient to prevent further programming of parasitic cells, while maintaining adequate channel boosting potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pass voltage is applied to adjacent word lines during programming, then channel boosting is maintained for programming operation, but parasitic cells are formed between memory cells causing program disturb
Solution Approach 1:
The patent applies different pass voltage levels to different adjacent word lines based on their position relative to the selected word line. Specifically, a first pass voltage level is applied to a first adjacent word line while a second, lower pass voltage level is applied to a second adjacent word line. This localized differentiation allows the system to maintain channel boosting where needed while minimizing parasitic cell formation in other regions, thereby resolving the contradiction between programming speed and program disturb.
Solution Approach 2:
The patent dynamically adjusts pass voltage parameters during the programming operation. By changing the voltage level applied to adjacent word lines based on programming progress and position, the system optimizes the balance between maintaining adequate channel boosting for efficient programming and reducing the voltage-induced parasitic effects that cause program disturb. This parameter optimization enables both high productivity and reduced harmful effects.
2Quantity of substance
If word line distance is scaled down to increase memory density, then memory capacity is improved, but parasitic cell formation increases due to stronger electric field coupling
Solution Approach 1:
The patent implements position-dependent pass voltage control where adjacent word lines at different positions relative to the selected word line receive different voltage levels. This local differentiation compensates for the increased electric field coupling caused by scaled-down word line distances, preventing excessive parasitic cell formation while maintaining the high memory density achieved through scaling.
3Productivity
If higher pass voltage is applied to maintain channel boosting, then programming efficiency is improved, but threshold voltage upshift increases in erased and lowest programmed state cells
Solution Approach 1:
The patent optimizes pass voltage parameters by applying different voltage levels to different adjacent word lines rather than using a uniform high voltage across all adjacent lines. This parameter differentiation allows the system to maintain adequate channel boosting for programming efficiency while limiting the excessive voltage exposure that causes threshold voltage upshift in erased and lowest programmed state cells, thereby resolving the contradiction between programming efficiency and threshold voltage control precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the widening of threshold voltage distributions for both erased and programmed states, reducing program disturb and maintaining accurate data states during read operations.
Implementation Method 1
The control circuit, to program selected memory cells connected to a selected word line (WLn) of the set of word lines, is configured to apply program voltages to the selected word line using incremental step pulse programming
Implementation Method 2
the first pass voltage initially exceeds the second pass voltage by a difference, and subsequently becomes progressively smaller during the incremental step pulse programming
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 2C
AI summary
Techniques are provided for preventing program disturb of unselected memory cells during programming of a selected memory cell in a NAND string which includes a continuous charge-trapping layer, either in a two-dimensional or three-dimensional configuration. In such a NAND string, regions between the memory cells can be inadvertently programmed as parasitic cells due to the program voltage and pass voltages on the word lines. For programmed cells, an upshift in threshold voltage due to a parasitic cell can be avoided by providing a higher pass voltage on an adjacent later-programmed word line than on an adjacent previously-programmed word line. For erased cells, an upshift in threshold voltage due to the parasitic cells can be reduced by progressively lowering the pass voltage on the adjacent later-programmed word line. The lowering can occur when memory cells of a lowest target data state complete programming.