Passing Gate Doping Layout to Minimize GIDL in Buried Gates
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Solution Overview
Problem
Gate-induced drain leakage (GIDL) in semiconductor devices increases operational unreliability due to the overlap of gate electrodes and junction regions, particularly exacerbated by the presence of passing gates in buried gate structures.
Innovation Solution
Implanting impurity ions or dopants into the gate electrode to tailor the doping profile and smooth the doping gradient of junction regions, reducing the effective electric field and minimizing GIDL, thereby enhancing operational reliability and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a passing gate is added to the semiconductor device, then the gate control capability is improved, but the gate-induced drain leakage (GIDL) increases
Solution Approach 1:
The patent applies local quality by creating a doped region specifically in the gate electrode tail portion that overlaps with the junction region. This localized doping modifies the electrical properties only in the critical area where GIDL occurs, while maintaining the overall gate control functionality. The doped region is formed at a specific location (the tail of the gate electrode) rather than uniformly across the entire gate structure.
Solution Approach 2:
The patent changes the doping parameter of the gate electrode by forming an additional doped region in the gate electrode tail. This modifies the carrier concentration and electrical characteristics of the gate electrode in the overlap region, thereby reducing the effective electric field and minimizing GIDL while preserving the passing gate's control capability.
2Quantity of substance
If the gate electrode overlaps with junction regions, then the device integration density is improved, but the operational reliability decreases due to increased GIDL
Solution Approach 1:
The patent maintains the overlapping structure for integration density while applying local quality modification through targeted doping in the gate electrode tail. This localized doped region specifically addresses the GIDL problem in the overlap area without changing the overall device layout or reducing integration density.
Solution Approach 2:
The patent converts the harmful effect of the gate-junction overlap (which causes GIDL) into a beneficial outcome by introducing a doped region that actively compensates for the overlap-induced leakage. The doped region transforms the problematic high-field region into a controlled region with modified electrical characteristics, thereby improving operational reliability while maintaining the space-efficient overlapping structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The additional doped region in the gate electrode reduces GIDL, preventing interference between word-lines and extending data retention time, thus improving the overall operational reliability of semiconductor devices.
Implementation Method 1
Implanting impurity ions or dopants into a gate electrode tailors the doping profile of the junction regions and smooths the doping gradient of the junction regions
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first trench in a substrate, disposing a first gate electrode in the first trench, and disposing a dummy gate electrode on the first gate electrode in the first trench. The method also includes removing the dummy gate electrode from the first gate electrode and forming a first doped region in the first gate electrode.