Semiconductor Passing Gate Vertical Separation for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing integration of semiconductor devices leads to increased capacitance between the bit line and gate, causing operational reliability issues due to Gate Induced Drain Leakage (GIDL) from the overlap region of the conventional buried gate structure, which deteriorates the retention characteristics of the semiconductor device.
Innovation Solution
A semiconductor device is fabricated with a structural modification where the junction region is spaced apart from the passing gate, and the gate conductive film is formed such that the operation gate is positioned higher than the passing gate, preventing overlap and reducing leakage current, and a step difference is created to increase the contact area between the junction region and the storage node contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional buried gate structure is used to reduce gate-electrode resistance, then device integration is improved, but Gate Induced Drain Leakage (GIDL) occurs due to overlap between junction and gate
Solution Approach 1:
The patent applies dimensionality change by forming the operation gate at a higher elevation than the passing gate, creating a vertical separation between the two gate structures. This height difference prevents the horizontal overlap between the operation gate and junction that causes GIDL, while maintaining the buried gate structure's low resistance benefit. The operation gate is positioned such that its bottom surface is higher than the top surface of the passing gate, effectively eliminating the harmful overlap region.
2Adaptability or versatility
If passing gates are formed in the device isolation film, then cell array functionality is improved, but leakage current increases due to overlap region
Solution Approach 1:
The patent applies local quality by creating different elevation levels for different gate regions. The passing gate is formed at a lower level within the device isolation film, while the operation gate is formed at a higher level within the active region. This localized height differentiation allows the passing gate to maintain its functionality for cell array operation while preventing it from causing GIDL when the operation gate is present, as the two gates operate at different vertical positions.
3Area of stationary object
If junction and gate are positioned close together, then device area is reduced, but contact resistance between junction and storage node contact increases
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension to separate the operation gate from the junction, allowing them to be positioned close in the horizontal plane without increasing contact resistance. The height difference ensures that the operation gate does not interfere with the electrical contact between the junction and storage node contact, while still maintaining compact horizontal spacing to minimize device area.
Data Source
AI summary
A semiconductor device includes passing gates. In the semiconductor device, a passing gate formed in a device isolation film is vertically positioned at a deeper and lower level than an operation gate formed in an active region defined by the device isolation film such that the passing gate does not overlap with a junction region. A step difference is formed in a storage node junction region, and thus a contact area between a storage node contact and the storage node junction region is increased, resulting in the improvement of operational characteristics of the semiconductor device.