Passivated Copper Chip Pads Trench Liner
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in reducing fabrication costs for flip chip packages due to the need for multiple lithographic steps and expensive masks, particularly in forming and passivating chip bonding pads.
Innovation Solution
The implementation of passivated copper chip pads with a conductive liner in trenches and an under bump metallization layer that directly contacts the last level of metallization, eliminating the need for chip bonding pads and reducing the number of mask steps by using a trench-based structure with a conductive liner and under bump metallization layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional chip bonding pads with multiple lithographic steps are used, then reliable electrical connection is achieved, but fabrication cost increases and manufacturing complexity increases
Solution Approach 1:
The patent extracts and eliminates the separate chip bonding pad structure from the metallization process. Instead of forming dedicated bonding pads through multiple lithographic steps, the design uses the last level of metallization directly as the bonding interface, covered by passivation with sidewall conductive liners. This extraction of the bonding pad function reduces fabrication complexity and cost while maintaining reliable electrical connection through the conductive liner-metallization-bump metal interface.
Solution Approach 2:
The last level of metallization serves multiple functions: it acts as both the electrical interconnection layer and the bonding pad interface. By making the metallization layer multi-functional, the patent eliminates the need for separate bonding pad structures and reduces the number of lithographic steps required, thereby lowering fabrication cost and complexity while ensuring reliable electrical connection.
2Manufacturing precision
If multiple lithographic steps and masks are used for forming chip bonding pads, then precise pad formation is achieved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent merges the bonding pad formation process with the passivation process. Instead of using separate lithographic steps to define bonding pads, the sidewall conductive liners formed during passivation serve as the bonding pad interfaces. This merging of functions reduces the number of mask steps and lithographic operations while maintaining precise alignment through the sidewall liner geometry, thereby reducing device complexity and fabrication cost.
Solution Approach 2:
The patent transitions from planar bonding pad definition to three-dimensional sidewall liner definition. By forming conductive liners on the sidewalls of passivation trenches, the bonding interface is defined in the vertical dimension rather than through planar lithographic patterning. This dimensional change eliminates the need for additional lithographic masks while maintaining precise geometric control through the trench sidewall profile.
3Ease of manufacture
If chip bonding pads are eliminated and under bump metallization directly contacts last level metallization, then fabrication cost reduces, but electrical connection stability may be affected
Solution Approach 1:
The patent introduces sidewall conductive liners as intermediary structures between the passivation layer and the last level of metallization. These conductive liners serve as both the bonding pad interface and a stable electrical connection medium. The liners provide a large surface area contact between the under bump metallization and the underlying metallization, ensuring stable electrical connection while eliminating the need for separate chip bonding pads, thereby reducing fabrication cost.
Solution Approach 2:
The bonding interface is constructed as a composite structure consisting of the sidewall conductive liner, the last level of metallization, and the under bump metallization layer. This composite structure combines multiple materials with complementary properties: the conductive liner provides adhesion and electrical conductivity, the metallization provides low-resistance electrical path, and the bump metal provides bonding capability. This composite approach ensures stable electrical connection while simplifying the overall structure and reducing fabrication cost.
Data Source
AI summary
A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.