Passivated Epitaxy for Metal-Insensitive FET Source-Drain Formation
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down planar devices like MOSFETs due to high power dissipation and metal contamination, which introduces device defects and performance issues in strained field effect transistors (FETs).
Innovation Solution
A semiconductor structure and method that includes forming a passivation layer to isolate metal residuals from chlorine during the fabrication of FETs, using a composition like silicon carbide or silicon germanium, and epitaxially growing source and drain features with a semiconductor material different from the substrate to prevent metal-assisted silicon etching and associated defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strained field effect transistor (FET) fabrication is performed using conventional methods, then device density and performance are improved, but metal contamination introduces device defects and performance issues
Solution Approach 1:
A passivation layer is introduced as an intermediary between metal residuals and chlorine-containing chemicals during FET fabrication. This passivation layer prevents direct contact between chlorine and metal contaminants, eliminating metal-assisted silicon etching while allowing the fabrication process to continue. The passivation layer acts as a protective barrier that mediates the interaction between harmful chemicals and contaminants.
Solution Approach 2:
The invention extracts and removes the harmful interaction between metal residuals and chlorine by introducing a passivation layer that isolates them. This separation takes out the problematic chemical reaction from the fabrication process, preventing metal-assisted silicon etching while maintaining the necessary fabrication steps.
2Productivity
If scaling down planar devices like MOSFETs is pursued to increase device density, then production efficiency increases, but power dissipation becomes relatively high
Solution Approach 1:
The invention changes material parameters by introducing a passivation layer with specific protective properties and using strained semiconductor materials in the source and drain regions. These parameter changes enable smaller device dimensions with improved carrier mobility, allowing higher device density while managing power dissipation through material optimization rather than单纯的 scaling.
3Ease of manufacture
If epitaxial growth is performed without a passivation layer, then fabrication process is simpler, but metal-assisted silicon etching occurs causing device defects
Solution Approach 1:
The passivation layer is formed preliminarily before the epitaxial growth step, in advance of potential metal-assisted silicon etching. This preliminary protective action prevents defects during subsequent fabrication steps while adding minimal complexity to the overall process. The passivation layer is prepared beforehand to protect against harmful interactions during the epitaxial growth and subsequent processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces defects and enhances the performance of FETs by preventing metal-assisted silicon etching and dopant diffusion, leading to improved carrier mobility and reduced leakage.
Implementation Method 1
forming a passivation layer to isolate metal residuals from chlorine during the fabrication of FETs
Implementation Method 2
epitaxially growing source and drain features with a semiconductor material different from the substrate
Data Source
AI summary
The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.