Passivation Protection for Semiconductor Interconnect Metal Lines

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Solution Overview

Problem

In semiconductor manufacturing, the formation of native oxides and contaminants on metal surfaces during queue time can lead to poor adhesion and electrical performance issues due to inadequate passivation protection, especially when using low dielectric constant materials in sub-micron interconnects.

Innovation Solution

A method involving the selective formation of a metal capping layer and a metal dielectric barrier layer, followed by a dielectric capping layer, within a multi-chamber processing system to minimize exposure to ambient conditions and prevent oxidation, using techniques like PVD and plasma treatment to enhance moisture resistance and interface quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the substrate is transferred among different vacuum environments during processing, then different processing steps can be performed, but the substrate is exposed to ambient environmental conditions during transfer, causing native oxide accumulation on the metal surface

Engineering Contradiction:
Improveprocessing flexibilityVSAvoidnative oxide accumulation
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

A passivation layer is introduced as an intermediary protective barrier between the metal surface and the ambient environment. This passivation layer prevents direct exposure of the metal to oxygen and water during chamber transfer, thereby preventing native oxide accumulation while allowing the substrate to be moved between different vacuum environments for various processing steps

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The passivation layer is formed in advance before the substrate is transferred between chambers. This preliminary protective action ensures that the metal surface is already protected against oxidation before exposure to ambient conditions during chamber transfer and before subsequent metallization processes

Inventive Principle:
Principle #10Preliminary action

2Object-affected harmful factors

If a metal containing passivation layer is used to cover the metal line, then exposure to atmosphere is minimized, but inadequate selection may result in insufficient moisture resistance or film degradation during plasma process

Engineering Contradiction:
Improveatmosphere exposure preventionVSAvoidmoisture resistance and plasma process stability
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The passivation structure uses a composite material system consisting of a metal-containing passivation layer combined with a dielectric bulk insulating material. This composite structure provides both the moisture resistance and plasma process stability required, with the metal layer providing oxidation prevention and the dielectric material providing moisture barrier and mechanical protection

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent specifies particular parameter ranges for the passivation layer including dielectric constant less than 4.0 and controlled thickness to ensure optimal performance. By carefully controlling these parameters, the passivation layer achieves both adequate moisture resistance and resistance to plasma process degradation

Inventive Principle:
Principle #35Parameter changes

3Productivity

If longer queue times are allowed for substrate transfer, then more processing steps can be performed, but thicker oxide layers form on the metal surface

Engineering Contradiction:
Improveprocessing throughputVSAvoidoxide layer thickness
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The passivation layer is applied in advance before the substrate enters the queue time period between chambers. This preliminary protection allows the substrate to remain protected during extended transfer and processing intervals, enabling longer queue times and higher productivity without the penalty of increased oxide accumulation

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces native oxide formation and contamination, maintaining good interface control and electrical performance by minimizing exposure to air, thereby increasing manufacturing flexibility without degrading device performance.

Implementation Method 1

selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system

Methodology Applied
Scientific EffectPhysical Vapor Deposition: Physical Vapour Deposition

Implementation Method 2

in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer

Methodology Applied
Scientific EffectIn-situ deposition: Physical Vapour Deposition

Implementation Method 3

using techniques like PVD and plasma treatment to enhance moisture resistance and interface quality

Methodology Applied
Scientific EffectPlasma treatment: Plasma

Data Source

PatentUS9299605B2Methods for forming passivation protection for an interconnection structure
Publication Date: 2016.03.29 APPLIED MATERIALS INC
  • US9299605B2 patent drawing
  • US9299605B2 patent drawing
  • US9299605B2 patent drawing

AI summary

Methods for forming a passivation protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming passivation protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system, in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer, and forming a dielectric capping layer on the barrier layer in the multi-chamber processing system.