Passivation Layer Surface Profiling for Planar 3D IC Bonding
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Solution Overview
Problem
The scaling down of semiconductor devices for 3DICs increases manufacturing complexity due to challenges in forming substantially planarized bonding layers with minimized surface height variations, leading to reduced bonding reliability between stacked IC chips.
Innovation Solution
The use of polish stop layers (PSLs) with higher polishing resistance than the bonding layer material, applied in peripheral regions to prevent edge roll-off during polishing, ensuring a planarized surface profile and increased bonding interface area between IC chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are scaled down to increase storage capacity and processing speed, then higher storage capacity and faster processing are achieved, but manufacturing complexity increases
Solution Approach 1:
The patent introduces a multi-layer structure with bonding layers, polish stop layers, and capping layers segmented into distinct functional regions (device regions and peripheral regions). This segmentation allows independent optimization of each layer's properties and processing parameters, managing the complexity introduced by scaling down device dimensions while maintaining high storage capacity.
Solution Approach 2:
The patent applies different material compositions and thicknesses to different regions of the bonding layer and polish stop layer. The bonding layer has different thicknesses in device regions versus peripheral regions, and the polish stop layer is selectively positioned to provide localized control over polishing rates. This local quality approach enables precise control of surface profile during scaling down manufacturing processes.
2Manufacturing precision
If bonding layer thickness is reduced to minimize surface height variations, then planarized surface area is improved, but bonding reliability decreases
Solution Approach 1:
The patent implements a bonding layer with non-uniform thickness, where the thickness varies between device regions and peripheral regions. This local quality variation allows the bonding layer to provide sufficient bonding reliability in critical device regions while maintaining minimal surface height variations in peripheral regions, thus resolving the contradiction between bonding strength and surface planarity.
Solution Approach 2:
The patent introduces a polish stop layer as an intermediary between the bonding layer and the polishing process. This intermediate layer with higher polishing resistance protects the bonding layer from excessive removal, allowing the bonding layer to be formed with precise thickness control that maintains both bonding reliability and surface planarity without direct exposure to aggressive polishing conditions.
3Manufacturing precision
If polishing is performed to planarize the bonding layer surface, then surface profile is improved, but edge roll-off occurs reducing bonding interface area
Solution Approach 1:
The patent forms a polish stop layer with higher polishing resistance before performing the polishing operation on the bonding layer. This preliminary action creates a protective barrier that prevents edge roll-off during polishing, allowing the bonding layer to be planarized without loss of bonding interface area, thus resolving the contradiction between surface profile quality and bonding area preservation.
Solution Approach 2:
The polish stop layer acts as an intermediary protective layer during the polishing process. It mediates between the polishing apparatus and the bonding layer, absorbing the mechanical stress and preventing direct contact that would cause edge roll-off. This intermediary layer enables achieving a planarized surface profile while maintaining the full bonding interface area intact.
4Reliability
If polish stop layers are added to prevent edge roll-off, then bonding reliability is improved, but device complexity increases
Solution Approach 1:
The patent designs the polish stop layer to serve multiple functions: it provides edge protection during polishing, acts as a depth reference for subsequent processing steps, and contributes to the overall structural integrity of the stacked IC. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity while achieving improved bonding reliability.
Solution Approach 2:
The patent combines the polish stop layer formation with other manufacturing steps, such as forming the layer during the same deposition process as other structural layers. By merging the polish stop layer creation with existing manufacturing operations rather than adding completely separate process steps, the increase in device complexity is minimized while still achieving the reliability benefits of edge roll-off prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of PSLs results in bonding layers with surface height variations of about 1 nm to 30 nm, enhancing the planarized surface area and bonding reliability between stacked IC chips in 3DICs by minimizing edge roll-off and increasing the effective bonding region.
Implementation Method 1
The use of polish stop layers (PSLs) with higher polishing resistance than the bonding layer material
Data Source
AI summary
An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.