Passivation Layer for Semiconductor Through Substrate Via Protection

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Solution Overview

Problem

Conventional semiconductor packaging technologies face challenges in preventing contamination from entering interconnect structures during through substrate via formation, which can damage metallization patterns and dielectric layers, leading to performance issues.

Innovation Solution

Incorporating a passivation layer, such as silicon nitride or undoped silicate glass, between the through substrate via and the interconnect or redistribution structure to block contaminants like moisture and chemicals, thereby protecting the metallization patterns and dielectric layers during the formation process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through substrate via formation is performed without a passivation layer, then the formation process is simpler and faster, but contamination enters the interconnect structures causing damage to metallization patterns and dielectric layers

Engineering Contradiction:

Improveintegrity of interconnect structureVSAvoidcomplexity of formation process

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

A passivation layer is deposited over the interconnect structure before through substrate via formation begins. This preliminary protective action prevents contamination from entering the interconnect structures during the via formation process, eliminating the need for complex in-process protection measures while ensuring structural integrity

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The passivation layer serves as an intermediary barrier between the contamination sources (etching chemicals, moisture) and the interconnect structures. This intermediate layer protects the sensitive metallization patterns and dielectric layers during the via formation process without interfering with the overall process simplicity

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If a passivation layer is added to protect interconnect structures, then contamination is blocked and reliability improves, but the manufacturing process becomes more complex

Engineering Contradiction:

Improveprotection of metallization patternsVSAvoidease of through via formation

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The passivation layer is deposited in advance before through via formation, simplifying the overall manufacturing process by eliminating the need for complex in-process protection measures. This preliminary protective action ensures that standard via formation procedures can be used without modification

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The protective function is extracted as a separate, standalone passivation layer that can be applied independently of the via formation process. This separation allows the via formation process to remain simple and standard while the protection function is provided by the pre-deposited passivation layer

Inventive Principle:

Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The passivation layer effectively prevents contamination from entering the interconnect structures, reducing damage to metallization patterns and enhancing the reliability and integrity of the semiconductor packaging.

Implementation Method 1

Methodology Applied

Scientific EffectPhysical barrier (passivation):

Data Source

PatentUS11658069B2Method for manufacturing a semiconductor device having an interconnect structure over a substrate

Publication Date: 2023.05.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.