Passivation Layer Protects Upper Electrode in MEMS Switch Etching

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Solution Overview

Problem

Existing semiconductor device manufacturing techniques face challenges in achieving consistent quality and reliability for MEMs switches due to sensitivity to etchants used in wet etching, which can damage the upper electrode pattern and affect manufacturing yield.

Innovation Solution

A semiconductor device manufacturing method that forms a passivation layer on the upper electrode pattern to protect it from etchant damage during wet etching, allowing for the formation of a cavity for a contact ball and improving the degrees of freedom of the upper electrode pattern while maintaining manufacturing yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If wet etching is used to form a cavity for the contact ball, then the cavity can be formed effectively, but the upper electrode pattern is damaged by the etchant

Engineering Contradiction:
Improvecavity formationVSAvoidupper electrode pattern integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A passivation layer is introduced as an intermediary protective layer between the upper electrode pattern and the etchant. This passivation layer is selectively removed in the cavity region to allow etching, while protecting the upper electrode pattern from etchant damage in other regions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The passivation layer is formed on the upper electrode pattern before the wet etching process. This preliminary protective action ensures that the upper electrode pattern is protected from etchant damage during the subsequent cavity formation process.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the upper electrode pattern is made insensitive to etchant, then reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveswitching action reliabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The passivation layer serves as a mediator that provides etchant insensitivity to the upper electrode pattern. This additional layer, while adding a step to the process, uses standard semiconductor fabrication techniques (oxidation or CVD) that do not significantly increase manufacturing complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The chemical properties of the upper electrode pattern are changed by forming a passivation layer through oxidation or chemical vapor deposition. This parameter change makes the upper electrode pattern insensitive to the etchant, improving reliability without requiring fundamentally new manufacturing techniques.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If a passivation layer is formed to protect the upper electrode pattern, then etchant damage is prevented, but additional manufacturing steps are required

Engineering Contradiction:
Improveelectrode pattern protectionVSAvoidmanufacturing cycle time
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The passivation layer is formed as a preliminary protective measure before the wet etching step. This allows the etching process to proceed without concern for upper electrode pattern damage, and the passivation layer can be selectively removed only where needed for cavity access.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The passivation layer is selectively removed in the cavity region while remaining intact in other regions. This local modification approach minimizes the impact on manufacturing cycle time by only adding protection where necessary and removing it only where needed for cavity formation.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution ensures the upper electrode pattern is insensitive to etchants, enhancing the reliability of switching actions and optimizing manufacturing yield by preventing damage to the electrode layers during the etching process.

Implementation Method 1

the step of forming a passivation layer may include the step of oxidizing at least a portion of a side of the upper electrode pattern to form the passivation layer

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS8765511B2Semiconductor device and method for manufacturing the same
Publication Date: 2014.07.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8765511B2 patent drawing
  • US8765511B2 patent drawing
  • US8765511B2 patent drawing

AI summary

A method for manufacturing a semiconductor device including at least one of the following steps: (1) Forming a lower electrode pattern on/over a substrate. (2) Forming a first interlayer insulating layer on the lower electrode pattern. (3) Forming an upper electrode pattern on the first interlayer insulating layer. (4) Forming a passivation layer on a side of the upper electrode pattern. (5) Forming a second interlayer insulating layer on the upper electrode pattern. (6) Etching the second interlayer insulating layer to form a cavity which exposes the passivation layer. (7) Forming a contact ball in the cavity.